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2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-2/+2
2020-07-13tcg/riscv: Remove superfluous breaksLiao Pingfang1-2/+0
2020-01-15tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé1-2/+2
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-10/+10
2019-07-09tcg/riscv: Fix RISC-VH host build failureAlistair Francis1-2/+2
2019-06-10cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson1-24/+7
2019-06-10tcg: Create struct CPUTLBRichard Henderson1-10/+2
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson1-2/+3
2019-04-24tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson1-4/+12
2019-04-24tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson1-0/+2
2019-01-28cputlb: Remove static tlb sizingRichard Henderson1-1/+0
2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson2-71/+55
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota1-0/+1
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis1-0/+111
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis1-0/+496
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis1-0/+158
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis1-0/+256
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis1-0/+145
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis1-0/+55
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis1-0/+65
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis1-0/+34
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis1-0/+86
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis1-0/+88
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis1-0/+48
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis1-0/+90
2018-12-26tcg/riscv: Add support for the constraintsAlistair Francis1-0/+168
2018-12-26tcg/riscv: Add the tcg target registersAlistair Francis1-0/+118
2018-12-26tcg/riscv: Add the tcg-target.h fileAlistair Francis1-0/+177
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