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AgeCommit message (Expand)AuthorFilesLines
2012-05-27tcg/ppc: Handle _CALL_DARWIN being undefined on DarwinAndreas Färber1-6/+10
2012-05-09tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 modeAndreas Färber1-1/+32
2012-05-09tcg/ppc: Clobber r5 for 64-bit qemu_ldAndreas Färber1-0/+3
2012-05-09tcg/ppc: Don't hardcode register numbersAndreas Färber1-12/+17
2012-05-09tcg/ppc: Do not overwrite lower address word on Darwin and AIXAndreas Färber1-4/+0
2012-05-03Bail out if CONFIG_TCG_PASS_AREG0 is definedmalc1-21/+1
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+45
2012-03-18i386: Remove REGPARMBlue Swirl1-1/+1
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-2/+2
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-4/+4
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-31tcg: TCG targets may define tcg_qemu_tb_execStefan Weil1-0/+4
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
2011-09-01tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warningsPeter Maydell1-10/+10
2011-08-22tcg/ppc32: implement deposit_i32malc2-1/+13
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-15/+16
2011-06-28TCG/PPC: use stack for TCG tempsBlue Swirl1-2/+5
2011-06-28tcg/ppc: Remove tcg_out_addimalc1-5/+0
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-3/+3
2010-08-15TCG: Fix Darwin/ppc calling convention recognitionAndreas Färber1-1/+1
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson1-4/+4
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-24/+24
2010-04-18tcg/ppc: Remove redundant comparison from brcond2malc1-2/+1
2010-04-17tcg/ppc: Fix signed versions of brcond2malc1-1/+2
2010-04-06tcg/ppc: Fix typomalc1-1/+1
2010-04-06tcg/ppc: Implment bswap16/32malc2-2/+77
2010-04-05tcg/ppc: Implement eqv, nand and normalc2-3/+17
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
2010-04-04tcg/ppc: Fix not_i32malc1-1/+1
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-3/+3
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+3
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
2010-02-23tcg/ppc: Fix typomalc1-1/+1
2010-02-22tcg/ppc: Implement some of the optional opsmalc2-8/+88
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad1-2/+0
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-1/+9
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
2010-02-20Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARG...Juergen Lock1-3/+3
2010-02-07tcg/ppc32: proper setcond implementationmalc1-25/+25
2010-02-07tcg/ppc32: implement setcond[2]malc1-14/+157
2009-09-27tcg/ppc: always use tcg_out_callmalc1-20/+10
2009-09-06When targeting PPU use rlwinm instead of andi. if possiblemalc1-8/+54
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