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AgeCommit message (Expand)AuthorFilesLines
2024-02-03tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson1-1/+2
2024-02-03tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson1-0/+2
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/mips: Implement neg opcodesRichard Henderson2-2/+10
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/mips: Always implement movcondRichard Henderson2-7/+16
2023-11-06tcg/mips: Split out tcg_out_setcond_intRichard Henderson1-172/+106
2023-10-22tcg/mips: Use tcg_use_softmmuRichard Henderson1-110/+105
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-2/+2
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson1-0/+5
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen1-1/+1
2023-08-24tcg: Introduce negsetcond opcodesRichard Henderson1-0/+2
2023-08-24tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson1-2/+1
2023-06-05tcg: Split out tcg-target-reg-bits.hRichard Henderson2-8/+18
2023-06-05tcg: Add tlb_fast_offset to TCGContextRichard Henderson1-3/+4
2023-06-05tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson1-5/+8
2023-05-30tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITSRichard Henderson1-1/+0
2023-05-25tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIANRichard Henderson1-26/+20
2023-05-25tcg/mips: Use qemu_build_not_reached for LO/HI_OFFRichard Henderson1-5/+3
2023-05-25tcg/mips: Try three insns with shift and add in tcg_out_moviRichard Henderson1-0/+44
2023-05-25tcg/mips: Try tb-relative addresses in tcg_out_moviRichard Henderson1-0/+13
2023-05-25tcg/mips: Aggressively use the constant pool for n64 callsRichard Henderson1-3/+13
2023-05-25tcg/mips: Use the constant pool for 64-bit constantsRichard Henderson2-17/+49
2023-05-25tcg/mips: Split out tcg_out_movi_twoRichard Henderson1-11/+24
2023-05-25tcg/mips: Split out tcg_out_movi_oneRichard Henderson1-6/+20
2023-05-25tcg/mips: Create and use TCG_REG_TBRichard Henderson1-10/+59
2023-05-25tcg/mips: Unify TCG_GUEST_BASE_REG testsRichard Henderson1-1/+1
2023-05-25tcg/mips: Move TCG_GUEST_BASE_REG to S7Richard Henderson1-2/+2
2023-05-25tcg/mips: Move TCG_AREG0 to S8Richard Henderson2-3/+3
2023-05-16tcg: Add page_bits and page_mask to TCGContextRichard Henderson1-3/+3
2023-05-16tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson1-19/+23
2023-05-16tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson1-24/+42
2023-05-16tcg/mips: Use atom_and_align_for_opcRichard Henderson1-6/+9
2023-05-16tcg: Add INDEX_op_qemu_{ld,st}_i128Richard Henderson1-0/+2
2023-05-16tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2-2/+5
2023-05-16tcg/mips: Use full load/store helpers in user-only modeRichard Henderson1-55/+2
2023-05-16tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson1-31/+0
2023-05-11tcg/mips: Simplify constraints on qemu_ld/stRichard Henderson3-32/+13
2023-05-11tcg/mips: Reorg tlb load within prepare_host_addrRichard Henderson1-20/+18
2023-05-11tcg/mips: Remove MO_BSWAP handlingRichard Henderson2-240/+48
2023-05-11tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_pathRichard Henderson1-132/+22
2023-05-11tcg/mips: Introduce prepare_host_addrRichard Henderson1-232/+172
2023-05-05tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}Richard Henderson1-91/+95
2023-05-02tcg/mips: Conditionalize tcg_out_exts_i32_i64Richard Henderson1-1/+3
2023-04-23tcg: Introduce tcg_out_xchgRichard Henderson1-0/+5
2023-04-23tcg: Split out tcg_out_extrl_i64_i32Richard Henderson1-3/+6
2023-04-23tcg: Split out tcg_out_extu_i32_i64Richard Henderson1-3/+6
2023-04-23tcg: Split out tcg_out_exts_i32_i64Richard Henderson1-1/+6
2023-04-23tcg: Split out tcg_out_ext32uRichard Henderson1-1/+2
2023-04-23tcg: Split out tcg_out_ext32sRichard Henderson1-3/+9
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