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path: root/tcg/mips/tcg-target.h
AgeCommit message (Expand)AuthorFilesLines
2014-05-12tcg-mips: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson1-0/+1
2014-04-18tcg: Use HOST_WORDS_BIGENDIANRichard Henderson1-4/+0
2014-04-18tcg: Relax requirement for mulu2_i32 on 32-bit hostsRichard Henderson1-0/+1
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
2013-09-03Merge branch 'tcg-next' of git://github.com/rth7680/qemuAurelien Jarno1-2/+3
2013-09-03tcg/mips: only enable ext8s/ext16s ops on MIPS32R2Aurelien Jarno1-2/+2
2013-09-03tcg/mips: detect available host instructions at runtimeAurelien Jarno1-21/+29
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-2/+1
2013-09-02tcg-mips: Implement mulsh, muluhRichard Henderson1-2/+2
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+2
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+1
2013-04-01tcg/mips: Implement muls2_i32Aurelien Jarno1-1/+1
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+1
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-3/+0
2012-09-26tcg/mips: fix MIPS32(R2) detectionAurelien Jarno1-4/+4
2012-09-22tcg/mips: implement movcond op on MIPS32R2Aurelien Jarno1-0/+8
2012-09-22tcg/mips: implement deposit op on MIPS32R2Aurelien Jarno1-1/+2
2012-09-22tcg/mips: implement rotl/rotr ops on MIPS32R2Aurelien Jarno1-1/+2
2012-09-22tcg/mips: optimize bswap{16,16s,32} on MIPS32R2Aurelien Jarno1-2/+9
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+1
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-1/+0
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-15/+16
2011-06-03Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.Brad1-0/+4
2010-04-14tcp/mips: Change TCG_AREG0 (fp -> s0)Stefan Weil1-1/+1
2010-04-05tcg/mips: use seb/seh instructions on MIPS32R2Aurelien Jarno1-2/+2
2010-03-27tcg-mips: add guest base supportAurelien Jarno1-0/+3
2010-03-27tcg-mips: implement norAurelien Jarno1-1/+1
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-1/+3
2009-12-01tcg: initial mips supportAurelien Jarno1-0/+104
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