aboutsummaryrefslogtreecommitdiff
path: root/tcg/loongarch64
AgeCommit message (Expand)AuthorFilesLines
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/loongarch64: Implement neg opcodesRichard Henderson2-2/+11
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/loongarch64: Use cpuinfo.hRichard Henderson2-11/+5
2023-11-06tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson2-7/+12
2023-10-22tcg/loongarch64: Use tcg_use_softmmuRichard Henderson1-65/+61
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-2/+2
2023-10-04tcg/loongarch64: Fix buid errorgaosong1-33/+35
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson1-0/+5
2023-09-16tcg/loongarch64: Implement 128-bit load & storeJiajie Chen3-1/+62
2023-09-15tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen2-1/+22
2023-09-15tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen2-1/+15
2023-09-15tcg/loongarch64: Lower vector shift integer opsJiajie Chen2-1/+22
2023-09-15tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen3-2/+12
2023-09-15tcg/loongarch64: Lower vector shift vector opsJiajie Chen2-1/+25
2023-09-15tcg/loongarch64: Lower vector saturated opsJiajie Chen2-1/+33
2023-09-15tcg/loongarch64: Lower vector min max opsJiajie Chen2-1/+33
2023-09-15tcg/loongarch64: Lower mul_vec to vmulJiajie Chen2-1/+9
2023-09-15tcg/loongarch64: Lower neg_vec to vnegJiajie Chen2-1/+9
2023-09-15tcg/loongarch64: Lower vector bitwise operationsJiajie Chen3-4/+50
2023-09-15tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen3-0/+63
2023-09-15tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen3-0/+67
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen1-1/+1
2023-09-15tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen5-2/+270
2023-09-15tcg/loongarch64: Import LSX instructionsJiajie Chen1-1/+6018
2023-08-24tcg: Introduce negsetcond opcodesRichard Henderson1-0/+3
2023-08-24tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson1-2/+1
2023-06-05tcg: Split out tcg-target-reg-bits.hRichard Henderson2-11/+21
2023-06-05tcg: Add tlb_fast_offset to TCGContextRichard Henderson1-3/+4
2023-06-05tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson1-0/+1
2023-05-16tcg: Add page_bits and page_mask to TCGContextRichard Henderson1-2/+2
2023-05-16tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson1-4/+5
2023-05-16tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson1-8/+16
2023-05-16tcg/loongarch64: Use atom_and_align_for_opcRichard Henderson1-1/+5
2023-05-16tcg: Add INDEX_op_qemu_{ld,st}_i128Richard Henderson1-0/+1
2023-05-16tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2-2/+5
2023-05-16tcg/loongarch64: Support softmmu unaligned accessesRichard Henderson1-7/+12
2023-05-16tcg/loongarch64: Check the host supports unaligned accessesRichard Henderson1-0/+9
2023-05-16tcg/loongarch64: Use full load/store helpers in user-only modeRichard Henderson1-30/+0
2023-05-16tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson1-23/+0
2023-05-11tcg/loongarch64: Simplify constraints on qemu_ld/stRichard Henderson3-22/+4
2023-05-11tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_pathRichard Henderson1-26/+11
2023-05-11tcg/loongarch64: Introduce prepare_host_addrRichard Henderson1-148/+103
2023-05-05tcg/loongarch64: Introduce HostAddressRichard Henderson1-25/+30
2023-05-05tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}Richard Henderson1-56/+40
2023-05-02tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64Richard Henderson1-1/+3
2023-04-23tcg: Introduce tcg_out_xchgRichard Henderson1-0/+5
2023-04-23tcg: Introduce tcg_out_movextRichard Henderson1-45/+8
2023-04-23tcg: Split out tcg_out_extrl_i64_i32Richard Henderson1-4/+6
2023-04-23tcg: Split out tcg_out_extu_i32_i64Richard Henderson1-4/+6
generated by cgit v1.1 at 2024-08-18 19:27:00 +0000