riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-10-12	tcg: Remove TCG_TARGET_HAS_GUEST_BASE define	Peter Maydell	1	-2/+0
2012-09-22	tcg-hppa: Implement movcond	Richard Henderson	1	-1/+1
2012-09-21	tcg: Introduce movcond	Richard Henderson	1	-0/+1
2012-09-15	Remove unused CONFIG_TCG_PASS_AREG0 and dead code	Blue Swirl	1	-1/+0
2012-03-03	w64: Change data type of parameters for flush_icache_range	Stefan Weil	1	-1/+3
2011-11-14	tcg: Standardize on TCGReg as the enum for hard registers	Richard Henderson	1	-2/+2
2011-10-01	tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h	Stefan Weil	1	-3/+1
2011-08-21	tcg: Always define all of the TCGOpcode enum members.	Richard Henderson	1	-13/+16
2011-07-01	tcg-hppa: Support deposit opcode.	Richard Henderson	1	-0/+1
2010-04-26	tcg-hppa: Remove automatically implemented opcodes.	Richard Henderson	1	-3/+5
2010-04-26	tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32.	Richard Henderson	1	-0/+2
2010-04-08	tcg-hppa: Fix in/out register overlap in add2/sub2.	Richard Henderson	1	-0/+1
2010-04-08	tcg-hppa: Finish the port.	Richard Henderson	1	-115/+27
2010-03-26	remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]	Paolo Bonzini	1	-2/+0
2010-03-14	tcg: add div/rem 32-bit helpers	Aurelien Jarno	1	-0/+1
2009-03-13	tcg: rename bswap_i32/i64 functions	aurel32	1	-1/+1
2009-03-08	Prune unused TCG_AREGs	blueswir1	1	-1/+0
2008-04-12	HPPA (PA-RISC) host support	aurel32	1	-0/+204