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AgeCommit message (Expand)AuthorFilesLines
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+1
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl2-29/+3
2012-08-26tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 codePeter Maydell1-93/+144
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+53
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-11/+11
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
2012-01-13tcg-arm: fix a typo in commentsAurelien Jarno1-1/+1
2012-01-10tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointerPeter Maydell1-1/+1
2011-12-14tcg/arm: remove fixed map code buffer restrictionDr. David Alan Gilbert1-19/+12
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-6/+7
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-01tcg/arm: Remove unused tcg_out_addi()Peter Maydell1-15/+0
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-14/+16
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-7/+10
2011-03-24tcg/arm: Support host code being compiled for ThumbPeter Maydell1-9/+26
2011-01-12tcg arm/mips/ia64: add a comment about retranslation and cachesAurelien Jarno1-0/+3
2011-01-10tcg/arm: improve constant loadingAurelien Jarno1-18/+21
2011-01-08tcg/arm: fix qemu_st64 for big endian targetsAurelien Jarno1-1/+1
2011-01-08tcg/arm: fix branch target change during code retranslationAurelien Jarno1-8/+20
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-1/+1
2010-04-25tcg/arm: fix condition in zero/sign extension functionsAurelien Jarno1-6/+6
2010-04-19tcg/arm: don't try to load constants using pcAurelien Jarno1-7/+0
2010-04-19tcg/arm: optimize register allocation orderAurelien Jarno1-5/+5
2010-04-19tcg/arm: fix argument alignment in qemu_st64Aurelien Jarno1-9/+10
2010-04-19tcg/arm: remove useless register tests in qemu_ld/stAurelien Jarno1-20/+10
2010-04-19tcg/arm: bswap arguments in qemu_ld/st if neededAurelien Jarno1-69/+159
2010-04-19tcg/arm: use ext* ops in qemu_ldAurelien Jarno1-18/+12
2010-04-19tcg/arm: remove conditional argument for qemu_ld/stAurelien Jarno1-51/+49
2010-04-19tcg/arm: add bswap opsAurelien Jarno2-2/+44
2010-04-19tcg/arm: add ext16u opAurelien Jarno2-20/+50
2010-04-19tcg/arm: add rotation opsAurelien Jarno2-1/+20
2010-04-19tcg/arm: use the blx instruction when possibleAurelien Jarno1-4/+12
2010-04-19tcg/arm: sxtb and sxth are available starting with ARMv6Aurelien Jarno1-2/+2
2010-04-19tcg/arm: add variables to define the allowed instructions setAurelien Jarno1-39/+84
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno1-0/+1
2010-04-19tcg/arm: replace integer values by registers enumAurelien Jarno1-109/+124
2010-04-19tcg/arm: remove store signed functionsAurelien Jarno1-62/+10
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno2-5/+11
2010-04-19tcg/arm: remove SAVE_LR codeAurelien Jarno1-43/+0
2010-03-28tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil1-1/+1
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-2/+2
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
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