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2023-07-10target/mips/mxu: Add S16MAD instructionSiarhei Volkau1-0/+65
2023-07-10target/mips/mxu: Add D16MADL instructionSiarhei Volkau1-0/+82
2023-07-10target/mips/mxu: Add D16MACF D16MACE instructionsSiarhei Volkau1-6/+68
2023-07-10target/mips/mxu: Add D16MULF D16MULE instructionsSiarhei Volkau1-5/+90
2023-07-10target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insnsSiarhei Volkau1-3/+293
2023-07-10target/mips/mxu: Add Q8ADD instructionSiarhei Volkau1-0/+77
2023-07-10target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insnsSiarhei Volkau1-1/+243
2023-07-10target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructionsSiarhei Volkau1-12/+18
2023-07-10target/mips/mxu: Add Q8SLT Q8SLTU instructionsSiarhei Volkau1-0/+65
2023-07-10target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructionsSiarhei Volkau2-7/+105
2023-07-10target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructionsSiarhei Volkau1-1/+82
2023-07-10target/mips: Add support of two XBurst CPUsSiarhei Volkau1-0/+46
2023-07-10target/mips: Add emulation of MXU instructions for 32-bit load/storeSiarhei Volkau1-23/+279
2023-07-10target/mips: Implement Loongson CSR instructionsJiaxun Yang14-0/+238
2023-07-10Merge tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/q...Richard Henderson16-128/+1966
2023-07-10target/mips: Rework cp0_timer with clock APIJiaxun Yang3-20/+26
2023-07-10target/s390x: Fix relative long instructions with large offsetsIlya Leoshkevich1-1/+1
2023-07-10target/s390x: Fix LRA when DAT is offIlya Leoshkevich1-1/+1
2023-07-10target/s390x: Fix LRA overwriting the top 32 bits on DAT errorIlya Leoshkevich3-4/+4
2023-07-10target/s390x: Fix MVCRL with a large value in R0Ilya Leoshkevich1-0/+1
2023-07-10target/s390x: Fix MDEB and MDEBRIlya Leoshkevich2-3/+4
2023-07-10target/s390x: Fix EPSW CC reportingIlya Leoshkevich1-0/+4
2023-07-10hw/s390x: Move KVM specific PV from hw/ to target/s390x/kvm/Philippe Mathieu-Daudé11-8/+465
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner7-0/+730
2023-07-10target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVMDaniel Henrique Barboza1-0/+70
2023-07-10target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helperDaniel Henrique Barboza1-4/+7
2023-07-10target/riscv: update multi-letter extension KVM propertiesDaniel Henrique Barboza1-0/+27
2023-07-10target/riscv/cpu.c: create KVM mock propertiesDaniel Henrique Barboza1-0/+36
2023-07-10target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()Daniel Henrique Barboza1-2/+1
2023-07-10target/riscv/cpu.c: add satp_mode properties earlierDaniel Henrique Barboza1-4/+2
2023-07-10target/riscv/kvm.c: add multi-letter extension KVM propertiesDaniel Henrique Barboza2-0/+127
2023-07-10target/riscv/kvm.c: update KVM MISA bitsDaniel Henrique Barboza1-0/+40
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza2-0/+83
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza2-29/+88
2023-07-10target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPUDaniel Henrique Barboza1-11/+23
2023-07-10target/riscv: handle mvendorid/marchid/mimpid for KVM CPUsDaniel Henrique Barboza1-0/+31
2023-07-10target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()Daniel Henrique Barboza1-0/+16
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza3-0/+92
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza1-7/+53
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza1-2/+32
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza1-1/+37
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza1-10/+25
2023-07-10target/riscv KVM_RISCV_SET_TIMER macro is not configured correctlyyang.zhang1-1/+1
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien1-1/+0
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li1-0/+7
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li4-0/+76
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li4-0/+77
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li6-6/+80
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li2-0/+23
2023-07-10target/riscv: Add RVV registers to logIvan Klokov1-1/+56
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