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2024-12-19target/i386: Reset TSCs of parked vCPUs too on VM resetMaciej S. Szmigiero1-0/+15
Since commit 5286c3662294 ("target/i386: properly reset TSC on reset") QEMU writes the special value of "1" to each online vCPU TSC on VM reset to reset it. However parked vCPUs don't get that handling and due to that their TSCs get desynchronized when the VM gets reset. This in turn causes KVM to turn off PVCLOCK_TSC_STABLE_BIT in its exported PV clock. Note that KVM has no understanding of vCPU being currently parked. Without PVCLOCK_TSC_STABLE_BIT the sched clock is marked unstable in the guest's kvm_sched_clock_init(). This causes a performance regressions to show in some tests. Fix this issue by writing the special value of "1" also to TSCs of parked vCPUs on VM reset. Reproducing the issue: 1) Boot a VM with "-smp 2,maxcpus=3" or similar 2) device_add host-x86_64-cpu,id=vcpu,node-id=0,socket-id=0,core-id=2,thread-id=0 3) Wait a few seconds 4) device_del vcpu 5) Inside the VM run: # echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable Observe the sched_clock_stable() value is 1. 6) Reboot the VM 7) Once the VM boots once again run inside it: # echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable Observe the sched_clock_stable() value is now 0. Fixes: 5286c3662294 ("target/i386: properly reset TSC on reset") Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Link: https://lore.kernel.org/r/5a605a88e9a231386dc803c60f5fed9b48108139.1734014926.git.maciej.szmigiero@oracle.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson9-10/+0
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19target/riscv: Do not abuse DEFINE_PROP_END_OF_LISTRichard Henderson1-6/+6
These are not arrays of Property and had no business using DEFINE_PROP_END_OF_LIST. Use plain { } instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-20-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19target/s390x: Use s390x_cpu_properties for system mode onlyRichard Henderson1-3/+3
Avoid the empty property list for user-only mode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-5-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19target/ppc: Remove empty property listRichard Henderson1-6/+0
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-4-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-15target/sparc: Constify all Property and PropertyInfoRichard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/s390x: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/riscv: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/mips: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/microblaze: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/i386: Constify all PropertyRichard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/hexagon: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/avr: Constify all PropertyRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15target/arm: Constify all PropertyRichard Henderson3-17/+17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-14Merge tag 'pull-target-arm-20241213' of ↵Stefan Hajnoczi17-5414/+3999
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Finish conversion of A64 decoder to decodetree * Use float_round_to_odd in helper_fcvtx_f64_to_f32 * Move TLBI insn emulation code out to its own source file * docs/system/arm: fix broken links, document undocumented properties * MAINTAINERS: correct an email address # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmdcYCcZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3usmD/9x6yTRxIK2mi0CjY0Bii89 # hL1Z3n2bxRDu+WoMcsQKXQM5RcixILJyMsnArOxI3D1bVEkAskuaVcXL0uS7Inq6 # EkEq8Z5lfRikAP698U2tzaGhKRiE4NT/cNgOoFLddkjqvZ1tq3sSbPcCudSWkP+u # Z3c5etP8llGNhokNhKmIifE/auxiFdPh8JRXHAF3KhNu4VOX7gNWnt4YZNhnV2XN # TsD+IxU9LCfI8pIFK95zBUIQT/361lIoiY/r7RpN21HeEuS+4wXT/Vfii6rEgsg5 # pNkPoxX/Tc+67l4wXzgoV/p2I1KZbJZ/s7Ta5wLmopidwi2EP9ETVcfTzKIF+PIJ # 08nozInD+fxlyGBezTRDmuIKiC4t1lVW8TP8znyp3TcSHFs5Q/iQY0uPACzoUVuE # chMIt4dD6NlMxOanWANbsVlF+ZPc8MVBMz3zHVbvkOiogoRQYjuDqQIQAhLbQolg # uC/ql79WnUe0IX1j9rcW7+DVNq/bObLCN89uSjigHO2bo5FKKr4pnOG/SaAyER5L # T/OHy1ACcxGNVIiUwKEDxdQ5iwcl+GEJfMfrpJHlTzxeZggL2lE0mcpXaHGLTzXV # K7fSOBI15T+aRqN0/29Rtsw8ayMV5/RmnanesPmC2VN86ZCE0OKGOcLEdaI+q3iT # CMxIsCUCpMM4WjbdJ69ZgQ== # =wQ1l # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Dec 2024 11:26:15 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20241213' of https://git.linaro.org/people/pmaydell/qemu-arm: (85 commits) target/arm: Simplify condition for tlbi_el2_cp_reginfo[] target/arm: Move RME TLB insns to tlb-insns.c target/arm: Move small helper functions to tlb-insns.c target/arm: Move the TLBI OS insns to tlb-insns.c. target/arm: Move TLBI range insns target/arm: Move AArch64 EL3 TLBI insns target/arm: Move the AArch64 EL2 TLBI insns target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[] target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c target/arm: Move some TLBI insns to their own source file MAINTAINERS: correct my email address docs/system/arm/virt: document missing properties docs/system/arm/xlnx-versal-virt: document ospi-flash property docs/system/arm/fby35: document execute-in-place property docs/system/arm/orangepi: update links target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32 target/arm: Convert FCVTL to decodetree target/arm: Convert URECPE and URSQRTE to decodetree target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-14Merge tag 'pull-hex-20241212' of https://github.com/quic/qemu into stagingStefan Hajnoczi24-294/+147
Remove HEX_DEBUG, EXCP/CAUSE fixes # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmdbtW4ACgkQGlSvuOVk # bDJTOxAArBX1tuF46hpqsUIENvfKEXgb64W9YjzPi4CsFM90FP/4zVkxoLVjkyxe # jhngUsgNc/p7gEGhW8/OGPVwYrvXdS486E32+l4Qv2E7lWR7nNP0PeNdVYUiZotB # hALWMAwUWVXy23gMFlzjIyuRBYtRNhjwP6aLmbyWVqNhVckhpiQRxlNmv5+0nLmi # 1mp92z6ziBJK4i8HX7Nm4ske4b0mHhtmkOZe8ulx+Ky3Ag+q1wptt+XIMnv7dTFT # w7RH22LBQaRX6OKShRYspnDyMWQUaUXP8t4clnNOp+aesUpVyAlaB4mXj/uaSNlZ # hX944xJoC3Qh5K5kh64nbnm8SpqRalwe7K0CvWEeVCRlO8uFmtI6IZ9hxuBnMl/v # cHc+yaM3FG0BnN3GtCJIsl2x/8qQBChqS9EOLNhAzsbeyedHUSJCbnPKGtf0ggnK # jwhsDEl/1jnZ+ZTZxT+bW1aAXvh/dowHDmz9joVdibnYNKdHox0ur1S0foZptFVQ # TkFLkZ0m3AqgxWc4fL5xUvrN6o8EbZjzhG+gVuCP8rQANX90L2rGp7neteDRMviE # V5D2a76iOor2qHwR6rc2Um0Kd6c8X0UUnDsBWW5TpqOvxfKsdbwfOI+c46+nZkGZ # riFeeYpISv3g8wVvLK9HoTr30D4hQox3wyl7Bn6w8QXvcrcLk8w= # =6vY4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Dec 2024 23:17:50 EST # gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32 # gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown] # gpg: aka "Brian Cain <bcain@kernel.org>" [unknown] # gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown] # gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown] # gpg: aka "bcain" [unknown] # gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47 # Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32 * tag 'pull-hex-20241212' of https://github.com/quic/qemu: target/hexagon: Make HVX vector args. restrict * target/hexagon: Use argparse in all python scripts target/hexagon: add enums for event, cause target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_* Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-13target/arm: Simplify condition for tlbi_el2_cp_reginfo[]Peter Maydell1-3/+1
We currently register the tlbi_el2_cp_reginfo[] TLBI insns if EL2 is implemented, or if EL3 and v8 is implemented. This is a copy of the logic used for el2_cp_reginfo[], but for the specific case of the TLBI insns we can simplify it. This is because we do not need the "if EL2 does not exist but EL3 does then EL2 registers should exist and be RAZ/WI" handling here: all our cpregs are for instructions, which UNDEF when EL3 exists and EL2 does not. Simplify the condition down to just "if EL2 exists". This is not a behaviour change because: * for AArch64 insns we marked them with ARM_CP_EL3_NO_EL2_UNDEF, which meant that define_arm_cp_regs() would ignore them if EL2 wasn't present * for AArch32 insns, the .access = PL2_W meant that if EL2 was not present the only way to get at them was from AArch32 EL3; but we have no CPUs which have ARM_FEATURE_V8 but start in AArch32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-11-peter.maydell@linaro.org
2024-12-13target/arm: Move RME TLB insns to tlb-insns.cPeter Maydell2-38/+45
Move the FEAT_RME specific TLB insns across to tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-10-peter.maydell@linaro.org
2024-12-13target/arm: Move small helper functions to tlb-insns.cPeter Maydell3-254/+220
The remaining functions that we temporarily made global are now used only from callsits in tlb-insns.c; move them across and make them file-local again. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-9-peter.maydell@linaro.org
2024-12-13target/arm: Move the TLBI OS insns to tlb-insns.c.Peter Maydell2-80/+80
Move the TLBI OS insns across to tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-8-peter.maydell@linaro.org
2024-12-13target/arm: Move TLBI range insnsPeter Maydell3-328/+333
Move the TLBI invalidate-range insns across to tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-7-peter.maydell@linaro.org
2024-12-13target/arm: Move AArch64 EL3 TLBI insnsPeter Maydell3-52/+62
Move the AArch64 EL3 TLBI insns from el3_cp_reginfo[] across to tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-6-peter.maydell@linaro.org
2024-12-13target/arm: Move the AArch64 EL2 TLBI insnsPeter Maydell3-55/+62
Move the AArch64 EL2 TLBI insn definitions that were in el2_cp_reginfo[] across to tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-5-peter.maydell@linaro.org
2024-12-13target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[]Peter Maydell3-171/+182
Move the AArch64 TLBI insns that are declared in v8_cp_reginfo[] into tlb-insns.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-4-peter.maydell@linaro.org
2024-12-13target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.cPeter Maydell4-77/+92
Move the AArch32 TLBI insns for AArch32 EL2 to tlbi_insn_helper.c. To keep this as an obviously pure code-movement, we retain the same condition for registering tlbi_el2_cp_reginfo that we use for el2_cp_reginfo. We'll be able to simplify this condition later, since the need to define the reginfo for EL3-without-EL2 doesn't apply for the TLBI ops specifically. This move brings all the uses of tlbimva_hyp_write() and tlbimva_hyp_is_write() back into a single file, so we can move those also, and make them file-local again. The helper alle1_tlbmask() is an exception to the pattern that we only need to make these functions global temporarily, because once this refactoring is complete it will be called by both code in helper.c (vttbr_write()) and by code in tlb-insns.c. We therefore put its prototype in a permanent home in internals.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-3-peter.maydell@linaro.org
2024-12-13target/arm: Move some TLBI insns to their own source filePeter Maydell6-220/+280
target/arm/helper.c is very large and unwieldy. One subset of code that we can pull out into its own file is the cpreg arrays and corresponding functions for the TLBI instructions. Because these are instructions they are only relevant for TCG and we can make the new file only be built for CONFIG_TCG. In this commit we move the AArch32 instructions from: not_v7_cp_reginfo[] v7_cp_reginfo[] v7mp_cp_reginfo[] v8_cp_reginfo[] into a new file target/arm/tcg/tlb-insns.c. A few small functions are used both by functions we haven't yet moved across and by functions we have already moved. We temporarily make these global with a prototype in cpregs.h; when the move of all TLBI insns is complete these will return to being file-local. For CONFIG_TCG, this is just moving code around. For a KVM only build, these cpregs will no longer be added to the cpregs hashtable for the CPU. However this should not be a behaviour change, because: * we never try to migration sync or otherwise include ARM_CP_NO_RAW cpregs * for migration we treat the kernel's list of system registers as the authoritative one, so these TLBI insns were never in it anyway The no-tcg stub of define_tlb_insn_regs() therefore does nothing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-2-peter.maydell@linaro.org
2024-12-13target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32Richard Henderson1-15/+5
Softfloat has native support for round-to-odd. Use it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241206031428.78634-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVTL to decodetreeRichard Henderson2-186/+18
Remove lookup_disas_fn, handle_2misc_widening, disas_simd_two_reg_misc, disas_data_proc_simd, disas_data_proc_simd_fp, disas_a64_legacy, as this is the final insn to be converted. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-70-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert URECPE and URSQRTE to decodetreeRichard Henderson2-134/+8
Remove handle_2misc_reciprocal as these were the last insns decoded by that function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-69-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrteRichard Henderson5-2/+48
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-68-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetreeRichard Henderson2-291/+53
Remove disas_simd_scalar_two_reg_misc and disas_simd_two_reg_misc_fp16 as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-67-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert handle_2misc_fcmp_zero to decodetreeRichard Henderson4-150/+138
This includes FCMEQ, FCMGT, FCMGE, FCMLT, FCMLE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-66-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVT* (vector, integer) to decodetreeRichard Henderson6-188/+102
Remove handle_2misc_64 as these were the last insns decoded by that function. Remove helper_advsimd_f16to[su]inth as unused; we now always go through helper_vfp_to[su]hh or a specialized vector function instead. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-65-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetreeRichard Henderson5-146/+32
Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-64-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert [US]CVTF (vector) to decodetreeRichard Henderson4-168/+67
Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-63-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Rename helper_gvec_vcvt_[hf][su] with _rzRichard Henderson3-12/+12
Emphasize that these functions use round-to-zero mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-62-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetreeRichard Henderson2-47/+8
Remove disas_simd_scalar_shift_imm as these were the last insns decoded by that function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-61-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert [US]CVTF (vector, integer) scalar to decodetreeRichard Henderson2-10/+31
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-60-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetreeRichard Henderson2-3/+20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-59-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVT* (vector, integer) scalar to decodetreeRichard Henderson2-77/+86
Arm silliness with naming, the scalar insns described as part of the vector instructions, as separate from the "regular" scalar insns which output to general registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-58-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FRINT* (vector) to decodetreeRichard Henderson2-111/+85
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-57-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FSQRT (vector) to decodetreeRichard Henderson2-19/+53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-56-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FABS, FNEG (vector) to decodetreeRichard Henderson2-30/+31
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-55-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Implement gen_gvec_fabs, gen_gvec_fnegRichard Henderson3-18/+22
Move the current implementation out of translate-neon.c, and extend to handle all element sizes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-54-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert SHLL to decodetreeRichard Henderson2-37/+40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-53-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVTXN to decodetreeRichard Henderson2-81/+24
Remove handle_2misc_narrow as this was the last insn decoded by that function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-52-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert FCVTN, BFCVTN to decodetreeRichard Henderson2-42/+52
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-51-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetreeRichard Henderson2-60/+102
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-50-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Introduce clear_vecRichard Henderson1-9/+12
In a couple of places, clearing the entire vector before storing one element is the easiest solution. Wrap that into a helper function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-49-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13target/arm: Remove helper_neon_{add,sub}l_u{16,32}Richard Henderson3-51/+11
These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-48-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-31 18:10:32 +0000