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2023-03-20target/s390x: Handle LLGFRL from non-aligned addressesIlya Leoshkevich2-4/+5
Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Handle LRL and LGFRL from non-aligned addressesIlya Leoshkevich2-8/+9
Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Handle LGRL from non-aligned addressesIlya Leoshkevich2-4/+5
Use MO_ALIGN and let do_unaligned_access() generate a specification exception. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Handle EXECUTE of odd addressesIlya Leoshkevich1-2/+10
Generate a specification exception in the helper before trying to fetch the instruction. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Handle branching to odd addressesIlya Leoshkevich1-0/+9
Let branching happen and try to generate a new translation block with an odd address. Generate a specification exception in cpu_get_tb_cpu_state(). Reported-by: Harold Grovesteen <h.grovsteen@tx.rr.com> Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230316164428.275147-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Fix EXECUTE of relative long instructionsIlya Leoshkevich3-1/+14
The code uses the wrong base for relative addressing: it should use the target instruction address and not the EXECUTE's address. Fix by storing the target instruction address in the new CPUS390XState member and loading it from the code generated by gen_ri2(). Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230316210751.302423-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Fix R[NOX]SBG with T=1Ilya Leoshkevich1-0/+4
RXSBG usage in the "filetests" test from the wasmtime testsuite makes tcg_reg_alloc_op() attempt to temp_load() a TEMP_VAL_DEAD temporary, causing an assertion failure: 0x01000a70: ec14 b040 3057 rxsbg %r1, %r4, 0xb0, 0x40, 0x30 OP after optimization and liveness analysis: ---- 0000000001000a70 0000000000000004 0000000000000006 rotl_i64 tmp2,r4,$0x30 dead: 1 2 pref=0xffff and_i64 tmp2,tmp2,$0x800000000000ffff dead: 1 pref=0xffff [xor_i64 tmp3,tmp3,tmp2 dead: 1 2 pref=0xffff] and_i64 cc_dst,tmp3,$0x800000000000ffff sync: 0 dead: 0 1 2 pref=0xffff mov_i64 psw_addr,$0x1000a76 sync: 0 dead: 0 1 pref=0xffff mov_i32 cc_op,$0x6 sync: 0 dead: 0 1 pref=0xffff call lookup_tb_ptr,$0x6,$1,tmp8,env dead: 1 pref=none goto_ptr tmp8 dead: 0 set_label $L0 exit_tb $0x7fffe809d183 ../tcg/tcg.c:3865: tcg fatal error The reason is that tmp3 does not have an initial value, which confuses the register allocator. This also affects the correctness of the results. Fix by assigning R1 to it. Exposed by commit e2e641fa3d5 ("tcg: Change default temp lifetime to TEMP_TB"). Fixes: d6c6372e186e ("target-s390: Implement R[NOX]SBG") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230316172205.281369-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Implement Early Exception RecognitionIlya Leoshkevich4-1/+45
Generate a specification exception if a reserved bit is set in the PSW mask or if the PSW address is out of bounds dictated by the addressing mode. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230315020408.384766-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20target/s390x: Fix LPSWIlya Leoshkevich1-10/+12
Currently LPSW does not invert the mask bit 12 and incorrectly copies the BA bit into the address. Fix by generating code similar to what s390_cpu_load_normal() does. Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230315020408.384766-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-17Merge tag 'trivial-branch-for-8.0-pull-request' of ↵Peter Maydell1-7/+7
https://gitlab.com/laurent_vivier/qemu into staging Trivial branch pull request 20230317 Fix doc Fix sh4 cpu log output # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmQUdowSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748ylwP/RisLo3XrvNBVuDW/cLh7vhFcaeSqEzH # /RfdJ0DeqreXQYiwqsUS+YrtBARpBwuvBk1RGg46chx3IZJp7fmfLjs0sSSiESsR # kL8tJqRFFdCXmpmUWQqmluiCEBLllq8uDHMaAyXh95V2VRt4vrR8K2x3GW0yrarS # 4BvMdTAJBmjjpXRZ+/NY88EEEqCHgliWTHm+JKLj7II5duUYZO+r0XpCQELFdHig # uEYOupSUm/H4X8VuKuqNG1YGUz9c8X7nYZ+lgKLNH/i8vco+dPSoL4fZvG1ts/NH # kcA+EdGNDJZdvhOUDlvebSIZ9uuVjxy4WD8CIJQ5A2LGSdmv4KUJjQWGBw/r5B/B # e+uhrFnXJPrRSytSohB0iEzlrETBHAzq1yzoc7TYy70SzHtBylR0Xxwxnaq2N9ux # k4wyeXF6toX49RiZ0UmoYO82vtPqg1LOsmYDYWKNzgWbRsTIVJAXuAwBAVIzOgJV # hs93YO3gCaIjh8n/V43VvQzborNhp0xf6Ch7F0cgD1klAAKX1ICX4Mn2Qj7tPmgh # GUsdTpleaFTpsKxgpNP1eU5QYtI9ZcGBhAhsSV9SSnrRsWo1dlppZJkUWEndIHGr # iUnP5OPLtWU5tM2WbVNb3pio/4xrzft3lu4DKH2IecZbBHF11FpK6f9mrlOagAz0 # V/3JSBg10dZQ # =3s21 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Mar 2023 14:17:48 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu: docs/sphinx/kerneldoc.py: Honour --enable-werror target/sh4: Honor QEMU_LOG_FILENAME with QEMU_LOG=cpu exec/memory: Fix kernel-doc warning Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-16target/sh4: Honor QEMU_LOG_FILENAME with QEMU_LOG=cpuIlya Leoshkevich1-7/+7
When using QEMU_LOG=cpu on sh4, QEMU_LOG_FILENAME is partially ignored. Fix by using qemu_fprintf() instead of qemu_printf() in the respective places. Fixes: 90c84c560067 ("qom/cpu: Simplify how CPUClass:cpu_dump_state() prints") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230316003411.129462-1-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-15Fix build without CONFIG_XEN_EMUMiroslav Rezanina1-0/+2
Upstream commit ddf0fd9ae1 "hw/xen: Support HVM_PARAM_CALLBACK_TYPE_GSI callback" added kvm_xen_maybe_deassert_callback usage to target/i386/kvm/kvm.c file without conditional preprocessing check. This breaks any build not using CONFIG_XEN_EMU. Protect call by conditional preprocessing to allow build without CONFIG_XEN_EMU. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Message-Id: <20230308130557.2420-1-mrezanin@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-03-14Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell57-2258/+1066
accel/tcg: Fix NB_MMU_MODES to 16 Balance of the target/ patchset which eliminates tcg_temp_free Balance of the target/ patchset which eliminates tcg_const # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQPcb0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV885AgAjDbg1soRBy0THf0X # CVXmQ4yYyUKAonZBL8Abt9yX01BhLFqEsrju3HiaLNOM9DbwWQ4gdvSrtAZ/K2YG # d6EvC+rJe79pr58MEEhqO4OO1ymp52amRHtEXva4vcKRNuM9WF5by/Hz2PsZyenG # ysaLBdddooA9SJeL7xYBMpKWFgUm3C8NzfaRfCBVcG94er9u8RUi0kx+drmOLw0g # vZ3Hekvi2I8Y5mWqvHeAIOsr8Md9PO3ezWxEteE4qsPNTTRfVD93oSGe9nNCYZTX # wWU51Vfv9GB6hOylAfMRIeCmkjks/gqLOGElsh1MaVovNDTXS5IKV/HgaLaocJHV # 2P81uQ== # =FpIY # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Mar 2023 18:55:57 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits) tcg: Drop tcg_const_* tcg: Drop tcg_const_*_vec target/tricore: Use min/max for saturate target/ppc: Avoid tcg_const_* in translate.c target/ppc: Fix gen_tlbsx_booke206 target/ppc: Rewrite trans_ADDG6S target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc target/ppc: Avoid tcg_const_* in fp-impl.c.inc target/ppc: Avoid tcg_const_* in vsx-impl.c.inc target/ppc: Avoid tcg_const_* in xxeval target/ppc: Avoid tcg_const_* in vmx-impl.c.inc target/ppc: Avoid tcg_const_i64 in do_vcntmb target/m68k: Use tcg_constant_i32 in gen_ea_mode target/arm: Avoid tcg_const_ptr in handle_rev target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn target/arm: Avoid tcg_const_* in translate-mve.c target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} target/arm: Improve trans_BFCI target/arm: Create gen_set_rmode, gen_restore_rmode ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-13target/tricore: Use min/max for saturateRichard Henderson1-11/+3
Use tcg_constant_i32 for the bounds. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in translate.cRichard Henderson1-70/+72
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Fix gen_tlbsx_booke206Richard Henderson1-4/+2
Fix incorrect read from rD. Avoid adding 0 when rA == 0. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Rewrite trans_ADDG6SRichard Henderson1-24/+26
Compute all carry bits in parallel instead of a loop. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.incRichard Henderson1-2/+2
All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in fp-impl.c.incRichard Henderson1-14/+12
All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in vsx-impl.c.incRichard Henderson1-14/+14
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in xxevalRichard Henderson1-3/+5
Initialize a new temp instead of tcg_const_*. Fix a pasto in a comment. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_* in vmx-impl.c.incRichard Henderson1-5/+5
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_i64 in do_vcntmbRichard Henderson1-10/+11
Compute both partial results separately and accumulate at the end, instead of accumulating in the middle. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/m68k: Use tcg_constant_i32 in gen_ea_modeRichard Henderson1-1/+1
Return a constant for an immediate input. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in handle_revRichard Henderson1-11/+15
Here it is not trivial to notice first initialization, so explicitly zero the temps. Use an array for the output, rather than separate tcg_rd/tcg_rd_hi variables. Fixes a bug by adding a missing clear_vec_high. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrnRichard Henderson1-2/+6
It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in disas_simd_zip_trnRichard Henderson1-20/+21
It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Use an array for the output, rather than separate tcg_res{l,h} variables. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_* in translate-mve.cRichard Henderson1-25/+29
All uses are in the context of an accumulator conditionally having a zero input. Split the rda variable to rda_{i,o}, and set rda_i to tcg_constant_foo(0) when required. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}Richard Henderson1-2/+4
This hides the implicit initialization of a variable. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Improve trans_BFCIRichard Henderson1-8/+6
Reorg temporary usage so that we can use tcg_constant_i32. tcg_gen_deposit_i32 already has a width == 32 special case, so remove the check here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Create gen_set_rmode, gen_restore_rmodeRichard Henderson4-48/+48
Split out common subroutines for handing rounding mode changes during translation. Use tcg_constant_i32 and tcg_temp_new_i32 instead of tcg_const_i32. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Consistently use ARMFPRounding during translationRichard Henderson3-20/+20
In preparation for extracting new helpers, ensure that the rounding mode is represented as ARMFPRounding and not FloatRoundMode. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Improve arm_rmode_to_sfRichard Henderson3-29/+18
Use proper enumeration types for input and output. Use a const array to perform the mapping, with an assert that the input is valid. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sfRichard Henderson1-4/+2
While this enumerator has been present since the first commit, it isn't ever used. The first actual use of round-to-odd came with SVE, which currently uses float_round_to_odd instead of the arm-specific enumerator. Amusingly, the comment about unhandled TIEAWAY has been out of date since the initial commit of translate-a64.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Use rmode >= 0 for need_rmodeRichard Henderson1-28/+6
Initialize rmode to -1 instead of keeping two variables. This is already used elsewhere in translate-a64.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/tricore: Avoid tcg_const_i32Richard Henderson1-63/+64
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/tricore: Drop some temp initializationRichard Henderson1-2/+2
The temp variables here are always set afterward; the initialization with a constant was discarded. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/tricore: Use setcondi instead of explicit allocationRichard Henderson1-5/+2
This removes the only use of temp. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/tricore: Rename t_off10 and use tcg_constant_i32Richard Henderson1-29/+27
While temp3 could simply be initialized with tcg_constant_i32, the renaming makes the purpose clearer. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/tricore: Split t_n as constant from temp as variableRichard Henderson1-128/+140
As required, allocate temp separately. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13tcg/sparc: Avoid tcg_const_tl in gen_edgeRichard Henderson1-8/+6
Push tcg_constant_tl into the shift argument directly. Since t1 no longer exists as a temp, replace with lo1, whose last use was just above. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/sh4: Avoid tcg_const_i32Richard Henderson1-13/+13
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/sh4: Avoid tcg_const_i32 for TAS.BRichard Henderson1-6/+3
Since we're assigning to cpu_sr_t in the end, use that as the intermediate temp as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/s390x: Avoid tcg_const_i64Richard Henderson1-10/+10
All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/rx: Avoid tcg_const_i32Richard Henderson1-16/+16
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/rx: Avoid tcg_const_i32 when new temp neededRichard Henderson1-6/+6
These three cases use a constant as first input, and then overwrite the temp in the output. Separate them. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/rx: Use cpu_psw_z as temp in flags computationRichard Henderson1-15/+13
Since PSW_Z = PSW_S, we can move that assignment to the end and use PSW_Z as a temporary while computing PSW_O. Use tcg_constant_i32 instead of tcg_const_i32. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/rx: Use tcg_gen_abs_i32Richard Henderson1-11/+1
Remove the local definition of rx_abs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Avoid tcg_const_i64 in do_vector_shift_quadRichard Henderson1-1/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/ppc: Split out gen_vx_vmul10Richard Henderson1-46/+49
Move the body out of this large macro. Use tcg_constant_i64. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-02-02 13:26:06 +0000