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2020-09-01
target/microblaze: Fix width of EDR
Richard Henderson
2
-7
/
+6
2020-09-01
target/microblaze: Fix width of BTR
Richard Henderson
2
-8
/
+6
2020-09-01
target/microblaze: Fix width of FSR
Richard Henderson
2
-7
/
+6
2020-09-01
target/microblaze: Fix width of ESR
Richard Henderson
4
-11
/
+11
2020-09-01
target/microblaze: Fix width of MSR
Richard Henderson
4
-29
/
+17
2020-09-01
target/microblaze: Fix width of PC and BTARGET
Richard Henderson
5
-63
/
+43
2020-09-01
target/microblaze: Split the cpu_SR array
Richard Henderson
1
-41
/
+65
2020-09-01
target/microblaze: Split out EDR from env->sregs
Richard Henderson
3
-16
/
+6
2020-09-01
target/microblaze: Split out BTR from env->sregs
Richard Henderson
4
-6
/
+9
2020-09-01
target/microblaze: Split out FSR from env->sregs
Richard Henderson
4
-8
/
+11
2020-09-01
target/microblaze: Split out ESR from env->sregs
Richard Henderson
5
-22
/
+24
2020-09-01
target/microblaze: Split out EAR from env->sregs
Richard Henderson
5
-11
/
+14
2020-09-01
target/microblaze: Split out MSR from env->sregs
Richard Henderson
6
-49
/
+51
2020-09-01
target/microblaze: Split out PC from env->sregs
Richard Henderson
7
-27
/
+32
2020-09-01
target/microblaze: Tidy gdbstub
Richard Henderson
1
-90
/
+99
2020-08-28
softfloat: Implement the full set of comparisons for float16
Kito Cheng
1
-25
/
+0
2020-08-28
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828'...
Peter Maydell
10
-398
/
+446
2020-08-28
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
Richard Henderson
3
-10
/
+81
2020-08-28
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
Richard Henderson
3
-0
/
+73
2020-08-28
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
Richard Henderson
3
-4
/
+45
2020-08-28
target/arm: Generalize inl_qrdmlah_* helper functions
Richard Henderson
1
-51
/
+29
2020-08-28
target/arm: Tidy SVE tszimm shift formats
Richard Henderson
1
-19
/
+16
2020-08-28
target/arm: Split out gen_gvec_ool_zz
Richard Henderson
1
-8
/
+12
2020-08-28
target/arm: Split out gen_gvec_ool_zzz
Richard Henderson
1
-35
/
+18
2020-08-28
target/arm: Split out gen_gvec_ool_zzp
Richard Henderson
1
-15
/
+14
2020-08-28
target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
Richard Henderson
3
-92
/
+32
2020-08-28
target/arm: Split out gen_gvec_ool_zzzp
Richard Henderson
1
-19
/
+16
2020-08-28
target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
Richard Henderson
1
-23
/
+8
2020-08-28
target/arm: Clean up 4-operand predicate expansion
Richard Henderson
1
-68
/
+43
2020-08-28
target/arm: Merge do_vector2_p into do_mov_p
Richard Henderson
1
-13
/
+6
2020-08-28
target/arm: Rearrange {sve,fp}_check_access assert
Richard Henderson
2
-11
/
+17
2020-08-28
target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
Richard Henderson
1
-19
/
+24
2020-08-28
target/arm: Split out gen_gvec_fn_zz
Richard Henderson
1
-9
/
+10
2020-08-28
target/arm: Fill in the WnR syndrome bit in mte_check_fail
Richard Henderson
1
-4
/
+5
2020-08-28
target/arm: Pass the entire mte descriptor to mte_check_fail
Richard Henderson
1
-5
/
+5
2020-08-28
target/arm: Clarify HCR_EL2 ARMCPRegInfo type
Philippe Mathieu-Daudé
1
-1
/
+0
2020-08-27
hvf: Move HVFState typedef to hvf.h
Eduardo Habkost
1
-2
/
+2
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
5
-6
/
+109
2020-08-25
target/riscv: Return the exception from invalid CSR accesses
Alistair Francis
2
-29
/
+35
2020-08-25
target/riscv: Support the v0.6 Hypervisor extension CRSs
Alistair Francis
2
-0
/
+43
2020-08-25
target/riscv: Only support little endian guests
Alistair Francis
1
-0
/
+5
2020-08-25
target/riscv: Only support a single VSXL length
Alistair Francis
1
-0
/
+9
2020-08-25
target/riscv: Update the CSRs to the v0.6 Hyp extension
Alistair Francis
1
-6
/
+8
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
4
-26
/
+9
2020-08-25
target/riscv: Fix the interrupt cause code
Alistair Francis
1
-2
/
+3
2020-08-25
target/riscv: Convert MSTATUS MTL to GVA
Alistair Francis
3
-9
/
+26
2020-08-25
target/riscv: Don't allow guest to write to htinst
Alistair Francis
1
-1
/
+0
2020-08-25
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
Alistair Francis
1
-35
/
+25
2020-08-25
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
6
-0
/
+474
2020-08-25
target/riscv: Allow setting a two-stage lookup in the virt status
Alistair Francis
3
-0
/
+21
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