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2020-09-01target/microblaze: Fix width of EDRRichard Henderson2-7/+6
2020-09-01target/microblaze: Fix width of BTRRichard Henderson2-8/+6
2020-09-01target/microblaze: Fix width of FSRRichard Henderson2-7/+6
2020-09-01target/microblaze: Fix width of ESRRichard Henderson4-11/+11
2020-09-01target/microblaze: Fix width of MSRRichard Henderson4-29/+17
2020-09-01target/microblaze: Fix width of PC and BTARGETRichard Henderson5-63/+43
2020-09-01target/microblaze: Split the cpu_SR arrayRichard Henderson1-41/+65
2020-09-01target/microblaze: Split out EDR from env->sregsRichard Henderson3-16/+6
2020-09-01target/microblaze: Split out BTR from env->sregsRichard Henderson4-6/+9
2020-09-01target/microblaze: Split out FSR from env->sregsRichard Henderson4-8/+11
2020-09-01target/microblaze: Split out ESR from env->sregsRichard Henderson5-22/+24
2020-09-01target/microblaze: Split out EAR from env->sregsRichard Henderson5-11/+14
2020-09-01target/microblaze: Split out MSR from env->sregsRichard Henderson6-49/+51
2020-09-01target/microblaze: Split out PC from env->sregsRichard Henderson7-27/+32
2020-09-01target/microblaze: Tidy gdbstubRichard Henderson1-90/+99
2020-08-28softfloat: Implement the full set of comparisons for float16Kito Cheng1-25/+0
2020-08-28Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828'...Peter Maydell10-398/+446
2020-08-28target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimdRichard Henderson3-10/+81
2020-08-28target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimdRichard Henderson3-0/+73
2020-08-28target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimdRichard Henderson3-4/+45
2020-08-28target/arm: Generalize inl_qrdmlah_* helper functionsRichard Henderson1-51/+29
2020-08-28target/arm: Tidy SVE tszimm shift formatsRichard Henderson1-19/+16
2020-08-28target/arm: Split out gen_gvec_ool_zzRichard Henderson1-8/+12
2020-08-28target/arm: Split out gen_gvec_ool_zzzRichard Henderson1-35/+18
2020-08-28target/arm: Split out gen_gvec_ool_zzpRichard Henderson1-15/+14
2020-08-28target/arm: Merge helper_sve_clr_* and helper_sve_movz_*Richard Henderson3-92/+32
2020-08-28target/arm: Split out gen_gvec_ool_zzzpRichard Henderson1-19/+16
2020-08-28target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_ppppRichard Henderson1-23/+8
2020-08-28target/arm: Clean up 4-operand predicate expansionRichard Henderson1-68/+43
2020-08-28target/arm: Merge do_vector2_p into do_mov_pRichard Henderson1-13/+6
2020-08-28target/arm: Rearrange {sve,fp}_check_access assertRichard Henderson2-11/+17
2020-08-28target/arm: Split out gen_gvec_fn_zzz, do_zzz_fnRichard Henderson1-19/+24
2020-08-28target/arm: Split out gen_gvec_fn_zzRichard Henderson1-9/+10
2020-08-28target/arm: Fill in the WnR syndrome bit in mte_check_failRichard Henderson1-4/+5
2020-08-28target/arm: Pass the entire mte descriptor to mte_check_failRichard Henderson1-5/+5
2020-08-28target/arm: Clarify HCR_EL2 ARMCPRegInfo typePhilippe Mathieu-Daudé1-1/+0
2020-08-27hvf: Move HVFState typedef to hvf.hEduardo Habkost1-2/+2
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis5-6/+109
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis2-29/+35
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2-0/+43
2020-08-25target/riscv: Only support little endian guestsAlistair Francis1-0/+5
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis1-0/+9
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis1-6/+8
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis4-26/+9
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis1-2/+3
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis3-9/+26
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis1-1/+0
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis1-35/+25
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis6-0/+474
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis3-0/+21