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2021-02-21target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2-0/+22
2021-02-21target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé1-1/+3
2021-02-21target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé3-27/+34
2021-02-21target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2-1/+2
2021-02-21target/mips: Include missing "tcg/tcg.h" headerPhilippe Mathieu-Daudé1-0/+1
2021-02-21target/mips: Remove unused 'rw' argument from page_table_walk_refill()Philippe Mathieu-Daudé1-3/+3
2021-02-21target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2-10/+10
2021-02-21target/mips: Let get_seg*_physical_address() take MMUAccessType argPhilippe Mathieu-Daudé1-5/+6
2021-02-21target/mips: Let get_physical_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-10/+10
2021-02-21target/mips: Let raise_mmu_exception() take MMUAccessType argumentPhilippe Mathieu-Daudé1-5/+5
2021-02-21target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2-4/+4
2021-02-21target/mips: Let do_translate_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-3/+4
2021-02-21target/mips: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2-2/+2
2021-02-21target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé1-16/+0
2021-02-21target/mips: Remove access_type argument from get_physical_address()Philippe Mathieu-Daudé1-13/+9
2021-02-21target/mips: Remove access_type arg from get_segctl_physical_address()Philippe Mathieu-Daudé1-10/+10
2021-02-21target/mips: Remove access_type argument from get_seg_physical_addressPhilippe Mathieu-Daudé1-3/+3
2021-02-21target/mips: Remove access_type argument from map_address() handlerPhilippe Mathieu-Daudé2-12/+11
2021-02-21target/mips: fetch code with translator_ldPhilippe Mathieu-Daudé1-10/+10
2021-02-20target/avr/cpu: Use device_class_set_parent_realize()Philippe Mathieu-Daudé1-3/+1
2021-02-18i386: Add the support for AMD EPYC 3rd generation processorsBabu Moger2-1/+110
2021-02-18Hexagon build infrastructureTaylor Simpson2-0/+192
2021-02-18Hexagon (target/hexagon) translationTaylor Simpson2-0/+841
2021-02-18Hexagon (target/hexagon) TCG for floating point instructionsTaylor Simpson1-0/+121
2021-02-18Hexagon (target/hexagon) TCG for instructions with multiple definitionsTaylor Simpson1-0/+198
2021-02-18Hexagon (target/hexagon) TCG generationTaylor Simpson2-0/+356
2021-02-18Hexagon (target/hexagon) instruction classesTaylor Simpson3-0/+174
2021-02-18Hexagon (target/hexagon) macrosTaylor Simpson1-0/+592
2021-02-18Hexagon (target/hexagon) opcode data structuresTaylor Simpson2-0/+200
2021-02-18Hexagon (target/hexagon) generater phase 4 - decode treeTaylor Simpson1-0/+351
2021-02-18Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode treeTaylor Simpson1-0/+188
2021-02-18Hexagon (target/hexagon) generator phase 2 - generate header filesTaylor Simpson10-0/+1565
2021-02-18Hexagon (target/hexagon) generator phase 1 - C preprocessor for semanticsTaylor Simpson1-0/+88
2021-02-18Hexagon (target/hexagon/imported) arch importTaylor Simpson14-0/+9236
2021-02-18Hexagon (target/hexagon/fma_emu.[ch]) utility functionsTaylor Simpson2-0/+738
2021-02-18Hexagon (target/hexagon/conv_emu.[ch]) utility functionsTaylor Simpson2-0/+208
2021-02-18Hexagon (target/hexagon/arch.[ch]) utility functionsTaylor Simpson2-0/+334
2021-02-18Hexagon (target/hexagon) instruction printingTaylor Simpson2-0/+173
2021-02-18Hexagon (target/hexagon) instruction/packet decodeTaylor Simpson2-0/+989
2021-02-18Hexagon (target/hexagon) instruction attributesTaylor Simpson2-0/+132
2021-02-18Hexagon (target/hexagon) register fieldsTaylor Simpson3-0/+104
2021-02-18Hexagon (target/hexagon) instruction and packet typesTaylor Simpson1-0/+74
2021-02-18Hexagon (target/hexagon) architecture typesTaylor Simpson1-0/+38
2021-02-18Hexagon (target/hexagon) GDB StubTaylor Simpson2-0/+49
2021-02-18Hexagon (target/hexagon) scalar core helpersTaylor Simpson2-0/+1152
2021-02-18Hexagon (target/hexagon) register namesTaylor Simpson1-0/+83
2021-02-18Hexagon (target/hexagon) scalar core definitionTaylor Simpson5-0/+599
2021-02-18Hexagon (target/hexagon) READMETaylor Simpson1-0/+235
2021-02-18target/sh4: Create superh_io_recompile_replay_branchRichard Henderson1-0/+18
2021-02-18target/mips: Create mips_io_recompile_replay_branchRichard Henderson1-0/+18