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AgeCommit message (Expand)AuthorFilesLines
2023-03-05target/xtensa: Tidy translate_clampsRichard Henderson1-4/+4
2023-03-05target/xtensa: Tidy translate_bbRichard Henderson1-11/+7
2023-03-05target/xtensa: Drop tcg_temp_freeRichard Henderson1-107/+0
2023-03-05target/xtensa: Drop reset_sar_trackerRichard Henderson1-12/+2
2023-03-01target/xtensa: Don't use tcg_temp_local_new_*Richard Henderson1-8/+8
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-02-27target/xtensa/cpu: Include missing "memory.h" headerPhilippe Mathieu-Daudé1-0/+3
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
2022-12-16target/xtensa: Convert to 3-phase resetPeter Maydell2-6/+10
2022-11-01accel/tcg: Remove will_exit argument from cpu_restore_stateRichard Henderson1-3/+3
2022-10-26target/xtensa: Convert to tcg_ops restore_state_to_opcRichard Henderson2-6/+10
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson1-0/+8
2022-09-13target/xtensa: Honour -semihosting-config userspace=onPeter Maydell1-3/+4
2022-09-13semihosting: Allow optional use of semihosting from userspacePeter Maydell1-3/+3
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+4
2022-05-11Clean up decorations and whitespace around header guardsMarkus Armbruster2-6/+2
2022-05-11Normalize header guard symbol definitionMarkus Armbruster1-1/+1
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster2-9/+6
2022-05-06target/xtensa: implement cache test option opcodesMax Filippov1-0/+38
2022-05-06target/xtensa: add clock input to xtensa CPUMax Filippov3-3/+24
2022-05-06target/xtensa: import core lx106Simon Safar5-0/+8273
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov1-52/+25
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov1-12/+6
2022-05-06target/xtensa: use tcg_constant_* for numbered special registersMax Filippov1-12/+4
2022-05-06target/xtensa: use tcg_constant_* for TLB opcodesMax Filippov1-8/+4
2022-05-06target/xtensa: use tcg_constant_* for exceptionsMax Filippov1-13/+5
2022-05-06target/xtensa: use tcg_contatnt_* for numeric literalsMax Filippov1-19/+9
2022-05-06target/xtensa: fix missing tcg_temp_free in gen_window_checkMax Filippov1-2/+2
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-3/+3
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau4-4/+0
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-0/+1
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau3-5/+5
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-1/+1
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2-4/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-4/+3
2022-03-06target: Use forward declared type instead of structure typePhilippe Mathieu-Daudé1-1/+1
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé6-0/+6
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-2/+2
2021-11-03Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson1-1/+1
2021-11-02target/xtensa: Make xtensa_cpu_tlb_fill sysemu onlyRichard Henderson3-23/+3
2021-10-31monitor: Trim some trailing space from human-readable outputMarkus Armbruster1-1/+1
2021-10-15target/xtensa: Drop check for singlestep_enabledRichard Henderson1-17/+8
2021-10-05target/xtensa: list cores in a text filePaolo Bonzini3-2/+14
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-2/+2
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-14target/xtensa: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé3-8/+5
2021-09-14target/xtensa: Restrict do_transaction_failed() to sysemuPhilippe Mathieu-Daudé1-0/+2
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-2/+3