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2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+6
2021-05-26cpu: Assert DeviceClass::vmsd is NULL on user emulationPhilippe Mathieu-Daudé1-1/+3
2021-05-20target/xtensa: clean up unaligned accessMax Filippov2-66/+67
2021-05-20target/xtensa: fix access ring in l32exMax Filippov1-1/+1
2021-05-20target/xtensa: don't generate extra EXCP_DEBUG on exceptionMax Filippov4-19/+0
2021-05-20target/xtensa: Make sure that tb->size != 0Ilya Leoshkevich1-0/+3
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2021-04-03target/xtensa: make xtensa_modules static on importMax Filippov1-0/+1
2021-04-03target/xtensa: fix meson.build rule for xtensa coresMax Filippov2-12/+4
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2-2/+2
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-7/+16
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2-3/+3
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: Move debug_excp_handler to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2020-11-15xtensa tcg cpus: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-11-13hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf1-1/+1
2020-10-26target/xtensa: enable all coprocessors for linux-userMax Filippov1-0/+1
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2-3/+3
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost1-1/+1
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost1-4/+2
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-6/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-3/+5
2020-08-21target/xtensa: import DSP3400 coreMax Filippov6-0/+173129
2020-08-21target/xtensa: import de233_fpu coreMax Filippov6-0/+22538
2020-08-21target/xtensa: implement FPU division and square rootMax Filippov3-0/+132
2020-08-21target/xtensa: add DFPU registers and opcodesMax Filippov6-34/+1413
2020-08-21target/xtensa: add DFPU optionMax Filippov2-0/+25
2020-08-21target/xtensa: don't access BR regfile directlyMax Filippov3-34/+42
2020-08-21target/xtensa: move FSR/FCR register accessorsMax Filippov1-32/+32
2020-08-21target/xtensa: rename FPU2000 translators and helpersMax Filippov3-55/+57
2020-08-21target/xtensa: support copying registers up to 64 bits wideMax Filippov2-5/+22
2020-08-21target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov3-10/+31
2020-08-21target/xtensa: implement NMI supportMax Filippov3-9/+21
2020-08-21target/xtensa: make opcode properties more dynamicMax Filippov2-265/+278
2020-08-21meson: targetPaolo Bonzini2-16/+30
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini21-17/+17
2020-06-25Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into stagingPeter Maydell3-23/+46
2020-06-22target/xtensa: drop gen_io_end callMax Filippov1-3/+0
2020-05-19softfloat: Name compare relation enumRichard Henderson1-3/+3
2020-05-17target/xtensa: fix simcall for newer hardwareMax Filippov1-3/+6
2020-05-17target/xtensa: fetch HW version from configuration overlayMax Filippov2-3/+6
2020-04-30target/xtensa: work around missing SR definitionsMax Filippov1-14/+34
2020-04-15gdbstub: Do not use memset() on GByteArrayPhilippe Mathieu-Daudé1-4/+2
2020-04-07target/xtensa: statically allocate xtensa_insnbufs in DisasContextMax Filippov3-16/+6