riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-05	accel/tcg: Introduce translator_io_start	Richard Henderson	1	-21/+6
2023-06-05	tcg: Pass TCGHelperInfo to tcg_gen_callN	Richard Henderson	1	-0/+4
2023-05-05	target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	1	-2/+2
2023-03-05	target/xtensa: Avoid tcg_const_i32	Richard Henderson	1	-3/+3
2023-03-05	target/xtensa: Split constant in bit shift	Richard Henderson	1	-4/+4
2023-03-05	target/xtensa: Use tcg_gen_subfi_i32 in translate_sll	Richard Henderson	1	-2/+2
2023-03-05	target/xtensa: Avoid tcg_const_i32 in translate_l32r	Richard Henderson	1	-3/+3
2023-03-05	target/xtensa: Tidy translate_clamps	Richard Henderson	1	-4/+4
2023-03-05	target/xtensa: Tidy translate_bb	Richard Henderson	1	-11/+7
2023-03-05	target/xtensa: Drop tcg_temp_free	Richard Henderson	1	-107/+0
2023-03-05	target/xtensa: Drop reset_sar_tracker	Richard Henderson	1	-12/+2
2023-03-01	target/xtensa: Don't use tcg_temp_local_new_*	Richard Henderson	1	-8/+8
2023-03-01	accel/tcg: Pass max_insn to gen_intermediate_code by pointer	Richard Henderson	1	-1/+1
2022-10-26	target/xtensa: Convert to tcg_ops restore_state_to_opc	Richard Henderson	1	-6/+0
2022-09-13	target/xtensa: Honour -semihosting-config userspace=on	Peter Maydell	1	-3/+4
2022-09-13	semihosting: Allow optional use of semihosting from userspace	Peter Maydell	1	-3/+3
2022-09-06	accel/tcg: Add pc and host_pc params to gen_intermediate_code	Richard Henderson	1	-2/+4
2022-05-06	target/xtensa: implement cache test option opcodes	Max Filippov	1	-0/+38
2022-05-06	target/xtensa: use tcg_constant_* for remaining opcodes	Max Filippov	1	-52/+25
2022-05-06	target/xtensa: use tcg_constant_* for FPU conversion opcodes	Max Filippov	1	-12/+6
2022-05-06	target/xtensa: use tcg_constant_* for numbered special registers	Max Filippov	1	-12/+4
2022-05-06	target/xtensa: use tcg_constant_* for TLB opcodes	Max Filippov	1	-8/+4
2022-05-06	target/xtensa: use tcg_constant_* for exceptions	Max Filippov	1	-13/+5
2022-05-06	target/xtensa: use tcg_contatnt_* for numeric literals	Max Filippov	1	-19/+9
2022-05-06	target/xtensa: fix missing tcg_temp_free in gen_window_check	Max Filippov	1	-2/+2
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson	1	-3/+4
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau	1	-3/+3
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot	1	-2/+2
2021-10-15	target/xtensa: Drop check for singlestep_enabled	Richard Henderson	1	-17/+8
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich	1	-2/+3
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson	1	-17/+0
2021-07-09	target/xtensa: Use translator_use_goto_tb	Richard Henderson	1	-5/+1
2021-07-09	tcg: Avoid including 'trace-tcg.h' in target translate.c	Philippe Mathieu-Daudé	1	-1/+0
2021-05-20	target/xtensa: clean up unaligned access	Max Filippov	1	-59/+61
2021-05-20	target/xtensa: fix access ring in l32ex	Max Filippov	1	-1/+1
2021-05-20	target/xtensa: don't generate extra EXCP_DEBUG on exception	Max Filippov	1	-6/+0
2021-05-20	target/xtensa: Make sure that tb->size != 0	Ilya Leoshkevich	1	-0/+3
2021-03-10	semihosting: Move include/hw/semihosting/ -> include/semihosting/	Philippe Mathieu-Daudé	1	-1/+1
2020-08-21	target/xtensa: implement FPU division and square root	Max Filippov	1	-0/+104
2020-08-21	target/xtensa: add DFPU registers and opcodes	Max Filippov	1	-23/+1103
2020-08-21	target/xtensa: don't access BR regfile directly	Max Filippov	1	-4/+16
2020-08-21	target/xtensa: move FSR/FCR register accessors	Max Filippov	1	-32/+32
2020-08-21	target/xtensa: rename FPU2000 translators and helpers	Max Filippov	1	-35/+35
2020-08-21	target/xtensa: support copying registers up to 64 bits wide	Max Filippov	1	-5/+21
2020-08-21	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov	1	-8/+27
2020-08-21	target/xtensa: make opcode properties more dynamic	Max Filippov	1	-261/+277
2020-06-22	target/xtensa: drop gen_io_end call	Max Filippov	1	-3/+0
2020-05-17	target/xtensa: fix simcall for newer hardware	Max Filippov	1	-3/+6
2020-04-30	target/xtensa: work around missing SR definitions	Max Filippov	1	-14/+34
2020-04-07	target/xtensa: statically allocate xtensa_insnbufs in DisasContext	Max Filippov	1	-16/+2