riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-06	target/xtensa: add clock input to xtensa CPU	Max Filippov	1	-3/+4
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth	1	-1/+0
2020-09-23	qemu/atomic.h: rename atomic_ to qatomic_	Stefan Hajnoczi	1	-1/+1
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov	1	-0/+42
2019-01-24	target/xtensa: fix access to the INTERRUPT SR	Max Filippov	1	-0/+2
2019-01-13	target/xtensa: move non-HELPER functions to helper.c	Max Filippov	1	-56/+0
2019-01-13	target/xtensa: drop dump_state helper	Max Filippov	1	-11/+0
2019-01-13	target/xtensa: extract interrupt and exception helpers	Max Filippov	1	-93/+0
2019-01-13	target/xtensa: extract debug helpers	Max Filippov	1	-92/+0
2019-01-13	target/xtensa: extract MMU helpers	Max Filippov	1	-293/+0
2019-01-13	target/xtensa: extract windowed registers helpers	Max Filippov	1	-190/+0
2019-01-13	target/xtensa: extract FPU helpers	Max Filippov	1	-135/+0
2019-01-11	target/xtensa: rework zero overhead loops implementation	Max Filippov	1	-24/+0
2018-10-01	target/xtensa: extract test for window underflow exception	Max Filippov	1	-9/+15
2018-10-01	target/xtensa: extract test for window overflow exception	Max Filippov	1	-5/+0
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	1	-37/+35
2018-09-17	target/xtensa: convert to do_transaction_failed	Max Filippov	1	-5/+7
2018-06-30	xtensa: Avoid calling get_page_addr_code() from helper function	Peter Maydell	1	-1/+5
2018-06-28	move public invalidate APIs out of translate-all.{c,h}, clean up	Paolo Bonzini	1	-8/+1
2018-05-31	Make tb_invalidate_phys_addr() take a MemTxAttrs argument	Peter Maydell	1	-1/+2
2018-04-11	icount: fix cpu_restore_state_from_tb for non-tb-exit cases	Pavel Dovgalyuk	1	-2/+2
2018-03-16	target/xtensa: add linux-user support	Max Filippov	1	-9/+41
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-0/+1
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-2/+2
2017-12-18	target/xtensa: pass actual frame size to the entry helper	Max Filippov	1	-1/+1
2017-09-26	target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macro	Alistair Francis	1	-2/+2
2017-03-09	target/xtensa: hold BQL for interrupt processing	Alex Bennée	1	-0/+7
2017-01-25	Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging	Peter Maydell	1	-8/+65
2017-01-16	target-xtensa: implement RER/WER instructions	Max Filippov	1	-0/+12
2017-01-15	target/xtensa: implement MEMCTL SR	Max Filippov	1	-0/+24
2017-01-15	target/xtensa: support icount	Max Filippov	1	-0/+4
2017-01-15	target/xtensa: refactor CCOUNT/CCOMPARE	Max Filippov	1	-8/+25
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2017-01-10	target-xtensa: Use clz opcode	Richard Henderson	1	-13/+0
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+984