riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-21	hw/core: Make do_unaligned_access noreturn	Richard Henderson	1	-2/+2
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-2/+0
2021-09-14	target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	1	-2/+2
2021-09-14	target/xtensa: Restrict do_transaction_failed() to sysemu	Philippe Mathieu-Daudé	1	-0/+2
2021-05-20	target/xtensa: don't generate extra EXCP_DEBUG on exception	Max Filippov	1	-7/+0
2020-08-21	target/xtensa: add DFPU registers and opcodes	Max Filippov	1	-0/+3
2020-08-21	target/xtensa: add DFPU option	Max Filippov	1	-0/+2
2020-08-21	target/xtensa: support copying registers up to 64 bits wide	Max Filippov	1	-0/+1
2020-08-21	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov	1	-1/+1
2020-08-21	target/xtensa: implement NMI support	Max Filippov	1	-0/+1
2020-08-21	target/xtensa: make opcode properties more dynamic	Max Filippov	1	-4/+1
2020-05-17	target/xtensa: fetch HW version from configuration overlay	Max Filippov	1	-0/+1
2020-04-07	target/xtensa: statically allocate xtensa_insnbufs in DisasContext	Max Filippov	1	-0/+3
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée	1	-1/+1
2020-01-15	target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX	Richard Henderson	1	-4/+0
2020-01-06	target/xtensa: fix ps.ring use in MPU configs	Max Filippov	1	-3/+7
2019-09-11	target/xtensa: linux-user: add call0 ABI support	Max Filippov	1	-0/+3
2019-08-20	configure: Define target access alignment in configure	tony.nguyen@bt.com	1	-2/+0
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson	1	-2/+0
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson	1	-0/+1
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson	1	-2/+0
2019-06-10	target/xtensa: Use env_cpu, env_archcpu	Richard Henderson	1	-11/+6
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	1	-2/+0
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-2/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	1	-16/+5
2019-05-21	Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging	Peter Maydell	1	-23/+35
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov	1	-0/+2
2019-05-15	target/xtensa: update list of exception causes	Max Filippov	1	-4/+5
2019-05-14	target/xtensa: implement DIWBUI.P opcode	Max Filippov	1	-0/+1
2019-05-10	target/xtensa: implement MPU option	Max Filippov	1	-0/+17
2019-05-10	target/xtensa: add parity/ECC option SRs	Max Filippov	1	-0/+6
2019-05-10	target/xtensa: define IDMA and gather/scatter IRQ types	Max Filippov	1	-0/+3
2019-05-10	target/xtensa: make internal MMU functions static	Max Filippov	1	-19/+0
2019-05-10	target/xtensa: get rid of centralized SR properties	Max Filippov	1	-0/+1
2019-05-10	target/xtensa: Convert to CPUClass::tlb_fill	Richard Henderson	1	-2/+3
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-2/+1
2019-04-18	target: Clean up how the dump_mmu() print	Markus Armbruster	1	-1/+1
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-1/+1
2019-02-28	target/xtensa: implement PREFCTL SR	Max Filippov	1	-0/+1
2019-02-28	target/xtensa: prioritize load/store in FLIX bundles	Max Filippov	1	-0/+4
2019-02-28	target/xtensa: reorganize register handling in translators	Max Filippov	1	-3/+12
2019-02-28	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	1	-0/+1
2019-02-28	target/xtensa: add generic instruction post-processing	Max Filippov	1	-0/+8
2019-02-28	target/xtensa: sort FLIX instruction opcodes	Max Filippov	1	-0/+2
2019-02-18	target/xtensa: allow multiple names for single opcode	Max Filippov	1	-1/+3
2019-02-18	target/xtensa: don't require opcode table sorting	Max Filippov	1	-2/+0
2019-02-18	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	1	-1/+0
2019-02-10	target/xtensa: don't specify windowed registers manually	Max Filippov	1	-1/+1