riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-02-28	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	1	-0/+1
2019-02-28	target/xtensa: add generic instruction post-processing	Max Filippov	1	-0/+8
2019-02-28	target/xtensa: sort FLIX instruction opcodes	Max Filippov	1	-0/+2
2019-02-18	target/xtensa: allow multiple names for single opcode	Max Filippov	1	-1/+3
2019-02-18	target/xtensa: don't require opcode table sorting	Max Filippov	1	-2/+0
2019-02-18	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	1	-1/+0
2019-02-10	target/xtensa: don't specify windowed registers manually	Max Filippov	1	-1/+1
2019-01-28	target/xtensa: expose core runstall as an IRQ line	Max Filippov	1	-0/+2
2019-01-28	target/xtensa: rearrange access to external interrupts	Max Filippov	1	-2/+3
2019-01-28	target/xtensa: drop function xtensa_timer_irq	Max Filippov	1	-1/+0
2019-01-11	target/xtensa: rework zero overhead loops implementation	Max Filippov	1	-0/+32
2018-10-01	target/xtensa: extract test for cpdisabled exception	Max Filippov	1	-0/+1
2018-10-01	target/xtensa: extract test for window overflow exception	Max Filippov	1	-0/+9
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	1	-1/+26
2018-09-17	target/xtensa: convert to do_transaction_failed	Max Filippov	1	-3/+4
2018-08-19	target/xtensa: clean up gdbstub register handling	Max Filippov	1	-0/+2
2018-06-30	target/xtensa: check zero overhead loop alignment	Max Filippov	1	-0/+1
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov	1	-2/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2018-03-16	target/xtensa: add linux-user support	Max Filippov	1	-19/+37
2018-03-13	target/xtensa: support MTTCG	Max Filippov	1	-0/+3
2018-03-13	target/xtensa: use correct number of registers in gdbstub	Max Filippov	1	-0/+1
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-1/+0
2018-01-22	target/xtensa: allow different default CPU for MMU/noMMU	Max Filippov	1	-1/+6
2018-01-09	target/xtensa: implement GPIO32	Max Filippov	1	-0/+1
2018-01-09	target/xtensa: add internal/noop SRs and opcodes	Max Filippov	1	-0/+2
2018-01-09	target/xtensa: use libisa for instruction decoding	Max Filippov	1	-0/+3
2017-12-18	target/xtensa: extract FPU2000 opcode translators	Max Filippov	1	-0/+1
2017-12-18	target/xtensa: extract core opcode translators	Max Filippov	1	-0/+24
2017-10-27	xtensa: cleanup cpu type name composition	Igor Mammedov	1	-0/+4
2017-09-01	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	1	-3/+1
2017-06-06	target/xtensa: support output to chardev console	Max Filippov	1	-0/+1
2017-02-23	target/xtensa: sim: instantiate local memories	Max Filippov	1	-0/+16
2017-01-16	target-xtensa: implement RER/WER instructions	Max Filippov	1	-0/+7
2017-01-15	target/xtensa: implement MEMCTL SR	Max Filippov	1	-0/+19
2017-01-15	target/xtensa: support icount	Max Filippov	1	-0/+5
2017-01-15	target/xtensa: refactor CCOUNT/CCOMPARE	Max Filippov	1	-5/+11
2017-01-15	target/xtensa: implement RUNSTALL	Max Filippov	1	-1/+2
2017-01-15	target/xtensa: add static vectors selection	Max Filippov	1	-1/+9
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+587