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path: root/target/xtensa/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2019-09-11target/xtensa: linux-user: add call0 ABI supportMax Filippov1-0/+3
2019-08-20configure: Define target access alignment in configuretony.nguyen@bt.com1-2/+0
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-2/+0
2019-06-10target/xtensa: Use env_cpu, env_archcpuRichard Henderson1-11/+6
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson1-16/+5
2019-05-21Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell1-23/+35
2019-05-15target/xtensa: implement exclusive access optionMax Filippov1-0/+2
2019-05-15target/xtensa: update list of exception causesMax Filippov1-4/+5
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov1-0/+1
2019-05-10target/xtensa: implement MPU optionMax Filippov1-0/+17
2019-05-10target/xtensa: add parity/ECC option SRsMax Filippov1-0/+6
2019-05-10target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov1-0/+3
2019-05-10target/xtensa: make internal MMU functions staticMax Filippov1-19/+0
2019-05-10target/xtensa: get rid of centralized SR propertiesMax Filippov1-0/+1
2019-05-10target/xtensa: Convert to CPUClass::tlb_fillRichard Henderson1-2/+3
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-2/+1
2019-04-18target: Clean up how the dump_mmu() printMarkus Armbruster1-1/+1
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster1-1/+1
2019-02-28target/xtensa: implement PREFCTL SRMax Filippov1-0/+1
2019-02-28target/xtensa: prioritize load/store in FLIX bundlesMax Filippov1-0/+4
2019-02-28target/xtensa: reorganize register handling in translatorsMax Filippov1-3/+12
2019-02-28target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov1-0/+1
2019-02-28target/xtensa: add generic instruction post-processingMax Filippov1-0/+8
2019-02-28target/xtensa: sort FLIX instruction opcodesMax Filippov1-0/+2
2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov1-1/+3
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov1-2/+0
2019-02-18target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov1-1/+0
2019-02-10target/xtensa: don't specify windowed registers manuallyMax Filippov1-1/+1
2019-01-28target/xtensa: expose core runstall as an IRQ lineMax Filippov1-0/+2
2019-01-28target/xtensa: rearrange access to external interruptsMax Filippov1-2/+3
2019-01-28target/xtensa: drop function xtensa_timer_irqMax Filippov1-1/+0
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov1-0/+32
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov1-0/+1
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov1-0/+9
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov1-1/+26
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov1-3/+4
2018-08-19target/xtensa: clean up gdbstub register handlingMax Filippov1-0/+2
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov1-0/+1
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-03-16target/xtensa: add linux-user supportMax Filippov1-19/+37
2018-03-13target/xtensa: support MTTCGMax Filippov1-0/+3
2018-03-13target/xtensa: use correct number of registers in gdbstubMax Filippov1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée1-1/+0
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