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2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (3/4)Philippe Mathieu-Daudé1-0/+3
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-14-philmd@linaro.org>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé1-1/+1
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson1-1/+0
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-15target/sparc: Constify all Property and PropertyInfoRichard Henderson1-2/+2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-12Merge tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi1-18/+8
tcg: Reset free_temps before tcg_optimize tcg/riscv: Fix StoreStore barrier generation include/exec: Introduce fpst alias in helper-head.h.inc target/sparc: Use memcpy() and remove memcpy32() # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmdbS7YdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9pFgf/RB1zSPYiID5psp+S # yL4raw8um4a3AbgI5g0wOY8PgIeN0anQxG0Yupo3Ka5rvhy9p7S36OOCJMFEJRbP # Sf2o4DG9Bqt6ycLh/mjQ8OqvL31T6f02GrkbUrevYVR7mYKjj+aJSbkIGKQqUOy3 # eptf9bbgtEe87oTXFZPxh24eEGE01WpHqDx3KQCCLlnsAR5ad9E8StWswu+8MiA/ # HttTGj8zqGu1N+wMtYfUuHtv8JdDK5H25gVbX/f+mLwNdWMXntsTw08Td3eY3EB0 # u44sEE+NSO04UiIu8U7NRrBNbUJsKautG90q4ZTOk5l8qVGIFWOP9kl0K1JjJZdd # jIR27g== # =+5lt # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Dec 2024 15:46:46 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu: target/sparc: Use memcpy() and remove memcpy32() include/exec: Introduce fpst alias in helper-head.h.inc tcg/riscv: Fix StoreStore barrier generation tcg: Reset free_temps before tcg_optimize Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-1/+1
* rust: better integration with clippy, rustfmt and rustdoc * rust: interior mutability types * rust: add a bit operations module * rust: first part of QOM rework * kvm: remove unnecessary #ifdef * clock: small cleanups, improve handling of Clock lifetimes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdZqFkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOzRwf/SYUD+CJCn2x7kUH/JG893jwN1WbJ # meGZ0PQDUpOZJFWg6T4g0MuW4O+Wevy2pF4SfGojgqaYxKBbTQVkeliDEMyNUxpr # vSKXego0K3pkX3cRDXNVTaXFbsHsMt/3pfzMQM6ocF9qbL+Emvx7Og6WdAcyJ4hc # lA17EHlnrWKUSnqN/Ow/pZXsa4ijCklXFFh4barfbdGVhMQc2QekUU45GsP2AvGT # NkXTQC05HqxBaAIDeSxbprDSzNihyT71dAooVoxqKboprPu5uoUSJwgaD8rADPr4 # EOfsz61V4mji+DWDcIzTtYoAdY41vVXI9lvCKOcCFkimA29xO0W6P7mG2w== # =JSh5 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 09:57:29 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (49 commits) rust: qom: change the parent type to an associated type rust: qom: split ObjectType from ObjectImpl trait rust: qom: move bridge for TypeInfo functions out of pl011 rust: qdev: move bridge for realize and reset functions out of pl011 rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro rust: qom: move ClassInitImpl to the instance side rust: qom: convert type_info! macro to an associated const rust: qom: rename Class trait to ClassInitImpl rust: qom: add default definitions for ObjectImpl rust: add a bit operation module rust: add bindings for interrupt sources rust: define prelude rust: cell: add BQL-enforcing RefCell variant rust: cell: add BQL-enforcing Cell variant bql: check that the BQL is not dropped within marked sections qom/object: Remove type_register() script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic ui: Replace type_register() with type_register_static() target/xtensa: Replace type_register() with type_register_static() target/sparc: Replace type_register() with type_register_static() ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12target/sparc: Use memcpy() and remove memcpy32()Philippe Mathieu-Daudé1-18/+8
Rather than manually copying each register, use the libc memcpy(), which is well optimized nowadays. Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241205205418.67613-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-11target/sparc: Set default NaN pattern explicitlyPeter Maydell1-0/+2
Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
2024-12-11target/sparc: Initialize local scratch float_status from env->fp_statusPeter Maydell3-8/+8
In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
2024-12-11target/sparc: Set Float3NaNPropRule explicitlyPeter Maydell1-0/+2
Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
2024-12-11target/sparc: Set FloatInfZeroNaNRule explicitlyPeter Maydell1-0/+2
Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
2024-12-10target/sparc: Replace type_register() with type_register_static()Zhao Liu1-1/+1
Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241029085934.2799066-13-zhao1.liu@intel.com
2024-11-05target/sparc: Explicitly set 2-NaN propagation rulePeter Maydell2-2/+16
Set the NaN propagation rule explicitly in the float_status words we use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241025141254.2141506-13-peter.maydell@linaro.org
2024-11-05target/sparc: Move cpu_put_fsr(env, 0) call to resetPeter Maydell1-1/+1
Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we later reset the CPU this will zero out all the fields up until the "end_reset_fields" label, which includes all of these (but not fp_status!) Move the cpu_put_fsr(env, 0) call to reset, because that expresses the logical requirement: we want to reset FSR to 0 on every reset. This isn't a behaviour change because the fields are all zero anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241025141254.2141506-12-peter.maydell@linaro.org
2024-09-20license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-laterPhilippe Mathieu-Daudé2-2/+2
The 'LGPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/LGPL-2.0+.html [2] https://spdx.org/licenses/LGPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/LGPL-2.0+/LGPL-2.0-or-later/ \ $(git grep -l 'SPDX-License-Identifier: LGPL-2.0+$') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-11target/sparc: Add gen_trap_if_nofpu_fpexceptionRichard Henderson1-29/+61
Model fp_exception state, in which only fp stores are allowed until such time as the FQ has been flushed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
2024-09-11target/sparc: Implement STDFQRichard Henderson2-3/+27
Invalid encoding of addr should raise TT_ILL_INSN, so check before supervisor, which might raise TT_PRIV_INSN. Clear QNE after execution. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
2024-09-11target/sparc: Add FSR_QNE to tb_flagsRichard Henderson2-4/+14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
2024-09-11target/sparc: Populate sparc32 FQ when raising fp exceptionCarl Hauser1-15/+25
Implement a single instruction floating point queue, populated while delivering an fp exception. Signed-off-by: Carl Hauser <chauser@pullman.com> [rth: Split from a larger patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
2024-09-11target/sparc: Add FQ and FSR.QNECarl Hauser3-0/+51
Add support for, and migrate, a single-entry fp instruction queue for sparc32. Signed-off-by: Carl Hauser <chauser@pullman.com> [rth: Split from a larger patch; adjust representation with union; add migration state] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
2024-08-20target/sparc: Restrict STQF to sparcv9Richard Henderson2-2/+2
Prior to sparcv9, the same encoding was STDFQ. Cc: qemu-stable@nongnu.org Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-23sparc/ldst_helper: make range overlap check more readableYao Xingtao1-3/+2
use ranges_overlap() instead of open-coding the overlap check to improve the readability of the code. Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240722040742.11513-9-yaoxt.fnst@fujitsu.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-11target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementationPeter Maydell1-0/+1
Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it is not set then the default is to call the CPUClass::has_work method (which has an identical function signature). We would like to make the cpu_exec_halt method mandatory so we can remove the runtime check and fallback handling. In preparation for that, make all the targets which don't need special handling in their cpu_exec_halt set it to their cpu_has_work implementation instead of leaving it unset. (This is every target except for arm and i386.) In the riscv case this requires us to make the function not be local to the source file it's defined in. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19target/sparc: use signed denominator in sdiv helperClément Chigot1-1/+1
The result has to be done with the signed denominator (b32) instead of the unsigned value passed in argument (b). Cc: qemu-stable@nongnu.org Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319 Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240606144331.698361-1-chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Enable VIS4 feature bitRichard Henderson1-0/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement monitor ASIsRichard Henderson3-0/+16
Ignore the "monitor" portion and treat them the same as their base ASIs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement MWAITRichard Henderson2-0/+12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement SUBXC, SUBXCccRichard Henderson2-0/+16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FPMIN, FPMAXRichard Henderson2-0/+28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement VIS4 comparisonsRichard Henderson4-47/+153
VIS4 completes the set, adding missing signed 8-bit ops and missing unsigned 16 and 32-bit ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUSRichard Henderson2-0/+20
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FALIGNDATAiRichard Henderson2-3/+31
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Add feature bit for VIS4Richard Henderson2-0/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement IMA extensionRichard Henderson4-0/+31
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Enable VIS3 feature bitRichard Henderson1-0/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement XMULXRichard Henderson4-0/+19
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement UMULXHIRichard Henderson2-0/+9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement PDISTNRichard Henderson2-0/+12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOdRichard Henderson2-0/+42
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement LZCNTRichard Henderson2-0/+19
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement LDXEFSRRichard Henderson4-2/+17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FSLL, FSRL, FSRA, FSLASRichard Henderson4-0/+58
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8Richard Henderson4-0/+58
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FPADDS, FPSUBSRichard Henderson2-0/+91
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FPADD64, FPSUB64Richard Henderson2-0/+5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FMEAN16Richard Henderson4-0/+53
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FLCMPRichard Henderson4-0/+86
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMULRichard Henderson4-0/+160
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement FCHKSM16Richard Henderson4-0/+57
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05target/sparc: Implement CMASK instructionsRichard Henderson4-0/+58
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-09-19 21:28:10 +0000