| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-05-15 | accel/tcg: Provide default implementation of disas_log | Richard Henderson | 1 | -9/+0 |
| 2024-05-05 | target/sparc: Fix FPMERGE | Richard Henderson | 1 | -1/+1 |
| 2024-05-05 | target/sparc: Fix FMULD8*X16 | Richard Henderson | 1 | -4/+44 |
| 2024-05-05 | target/sparc: Fix FMUL8x16A{U,L} | Richard Henderson | 1 | -4/+34 |
| 2024-05-05 | target/sparc: Fix FMUL8x16 | Richard Henderson | 1 | -1/+20 |
| 2024-05-05 | target/sparc: Fix FEXPAND | Richard Henderson | 1 | -1/+19 |
| 2024-04-12 | target/sparc: Use GET_ASI_CODE for ASI_KERNELTXT and ASI_USERTXT | Richard Henderson | 1 | -2/+46 |
| 2024-03-12 | target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro | Philippe Mathieu-Daudé | 1 | -6/+3 |
| 2024-02-15 | target/sparc: implement asr17 feature for smp | Clément Chigot | 1 | -10/+3 |
| 2024-02-03 | target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc | Richard Henderson | 1 | -2/+2 |
| 2024-02-03 | target/sparc: Split fcc out of env->fsr | Richard Henderson | 1 | -387/+110 |
| 2024-02-03 | target/sparc: Remove cpu_fsr | Richard Henderson | 1 | -48/+50 |
| 2024-02-03 | target/sparc: Split cexc and ftt from env->fsr | Richard Henderson | 1 | -11/+20 |
| 2024-02-03 | target/sparc: Merge check_ieee_exceptions with FPop helpers | Richard Henderson | 1 | -14/+0 |
| 2024-02-03 | target/sparc: Clear cexc and ftt in do_check_ieee_exceptions | Richard Henderson | 1 | -16/+0 |
| 2024-02-03 | target/sparc: Introduce cpu_get_fsr, cpu_put_fsr | Richard Henderson | 1 | -1/+6 |
| 2024-02-03 | target/sparc: Use i128 for Fdmulq | Richard Henderson | 1 | -11/+4 |
| 2024-02-03 | target/sparc: Use i128 for FdTOq, FxTOq | Richard Henderson | 1 | -4/+5 |
| 2024-02-03 | target/sparc: Use i128 for FsTOq, FiTOq | Richard Henderson | 1 | -4/+5 |
| 2024-02-03 | target/sparc: Use i128 for FCMPq, FCMPEq | Richard Henderson | 1 | -34/+20 |
| 2024-02-03 | target/sparc: Use i128 for FqTOd, FqTOx | Richard Henderson | 1 | -3/+4 |
| 2024-02-03 | target/sparc: Use i128 for FqTOs, FqTOi | Richard Henderson | 1 | -3/+4 |
| 2024-02-03 | target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq | Richard Henderson | 1 | -6/+7 |
| 2024-02-03 | target/sparc: Use i128 for FSQRTq | Richard Henderson | 1 | -5/+7 |
| 2024-02-03 | target/sparc: Inline FNEG, FABS | Richard Henderson | 1 | -32/+30 |
| 2024-02-03 | target/sparc: Introduce gen_{load,store}_fpr_Q | Richard Henderson | 1 | -6/+19 |
| 2024-02-03 | target/sparc: Remove gen_dest_fpr_F | Richard Henderson | 1 | -11/+6 |
| 2024-02-03 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL | Richard Henderson | 1 | -16/+15 |
| 2024-02-03 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY | Richard Henderson | 1 | -19/+26 |
| 2024-01-29 | target: Use vaddr in gen_intermediate_code | Anton Johansson | 1 | -1/+1 |
| 2023-11-14 | target/sparc: Fix RETURN | Richard Henderson | 1 | -1/+1 |
| 2023-11-05 | target/sparc: Check for invalid cond in gen_compare_reg | Richard Henderson | 1 | -19/+26 |
| 2023-11-05 | target/sparc: Implement UDIV inline | Richard Henderson | 1 | -13/+54 |
| 2023-11-05 | target/sparc: Implement UDIVX and SDIVX inline | Richard Henderson | 1 | -14/+95 |
| 2023-11-05 | target/sparc: Discard cpu_cond at the end of each insn | Richard Henderson | 1 | -0/+27 |
| 2023-11-05 | target/sparc: Record entire jump condition in DisasContext | Richard Henderson | 1 | -11/+16 |
| 2023-11-05 | target/sparc: Merge gen_op_next_insn into only caller | Richard Henderson | 1 | -7/+2 |
| 2023-11-05 | target/sparc: Pass displacement to advance_jump_cond | Richard Henderson | 1 | -7/+5 |
| 2023-11-05 | target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond | Richard Henderson | 1 | -44/+30 |
| 2023-11-05 | target/sparc: Merge gen_branch2 into advance_pc | Richard Henderson | 1 | -14/+14 |
| 2023-11-05 | target/sparc: Do flush_cond in advance_jump_cond | Richard Henderson | 1 | -6/+4 |
| 2023-11-05 | target/sparc: Always copy conditions into a new temporary | Richard Henderson | 1 | -1/+2 |
| 2023-11-05 | target/sparc: Change DisasCompare.c2 to int | Richard Henderson | 1 | -15/+18 |
| 2023-11-05 | target/sparc: Remove DisasCompare.is_bool | Richard Henderson | 1 | -15/+7 |
| 2023-11-05 | target/sparc: Remove CC_OP leftovers | Richard Henderson | 1 | -89/+26 |
| 2023-11-05 | target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV | Richard Henderson | 1 | -2/+2 |
| 2023-11-05 | target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB | Richard Henderson | 1 | -155/+42 |
| 2023-11-05 | target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD | Richard Henderson | 1 | -160/+87 |
| 2023-11-05 | target/sparc: Remove CC_OP_DIV | Richard Henderson | 1 | -12/+58 |
| 2023-11-05 | target/sparc: Remove CC_OP_LOGIC | Richard Henderson | 1 | -39/+27 |
