| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-05 | target/sparc: Implement VIS4 comparisons | Richard Henderson | 1 | -6/+6 |
| 2024-06-05 | target/sparc: Implement XMULX | Richard Henderson | 1 | -0/+2 |
| 2024-06-05 | target/sparc: Implement LDXEFSR | Richard Henderson | 1 | -0/+1 |
| 2024-06-05 | target/sparc: Implement FSLL, FSRL, FSRA, FSLAS | Richard Henderson | 1 | -0/+2 |
| 2024-06-05 | target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 | Richard Henderson | 1 | -0/+4 |
| 2024-06-05 | target/sparc: Implement FMEAN16 | Richard Henderson | 1 | -0/+1 |
| 2024-06-05 | target/sparc: Implement FLCMP | Richard Henderson | 1 | -0/+2 |
| 2024-06-05 | target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL | Richard Henderson | 1 | -0/+5 |
| 2024-06-05 | target/sparc: Implement FCHKSM16 | Richard Henderson | 1 | -0/+1 |
| 2024-06-05 | target/sparc: Implement CMASK instructions | Richard Henderson | 1 | -0/+3 |
| 2024-06-05 | target/sparc: Implement FMAf extension | Richard Henderson | 1 | -0/+2 |
| 2024-05-05 | target/sparc: Fix FPMERGE | Richard Henderson | 1 | -1/+1 |
| 2024-05-05 | target/sparc: Fix FMULD8*X16 | Richard Henderson | 1 | -2/+0 |
| 2024-05-05 | target/sparc: Fix FMUL8x16A{U,L} | Richard Henderson | 1 | -2/+1 |
| 2024-05-05 | target/sparc: Fix FMUL8x16 | Richard Henderson | 1 | -1/+1 |
| 2024-05-05 | target/sparc: Fix FEXPAND | Richard Henderson | 1 | -1/+1 |
| 2024-04-12 | target/sparc: Use GET_ASI_CODE for ASI_KERNELTXT and ASI_USERTXT | Richard Henderson | 1 | -0/+3 |
| 2024-02-15 | target/sparc: implement asr17 feature for smp | Clément Chigot | 1 | -0/+1 |
| 2024-02-03 | target/sparc: Split fcc out of env->fsr | Richard Henderson | 1 | -27/+7 |
| 2024-02-03 | target/sparc: Remove cpu_fsr | Richard Henderson | 1 | -60/+60 |
| 2024-02-03 | target/sparc: Split cexc and ftt from env->fsr | Richard Henderson | 1 | -1/+1 |
| 2024-02-03 | target/sparc: Merge check_ieee_exceptions with FPop helpers | Richard Henderson | 1 | -60/+59 |
| 2024-02-03 | target/sparc: Introduce cpu_get_fsr, cpu_put_fsr | Richard Henderson | 1 | -0/+1 |
| 2024-02-03 | target/sparc: Use i128 for Fdmulq | Richard Henderson | 1 | -1/+1 |
| 2024-02-03 | target/sparc: Use i128 for FdTOq, FxTOq | Richard Henderson | 1 | -2/+2 |
| 2024-02-03 | target/sparc: Use i128 for FsTOq, FiTOq | Richard Henderson | 1 | -2/+2 |
| 2024-02-03 | target/sparc: Use i128 for FCMPq, FCMPEq | Richard Henderson | 1 | -8/+8 |
| 2024-02-03 | target/sparc: Use i128 for FqTOd, FqTOx | Richard Henderson | 1 | -2/+2 |
| 2024-02-03 | target/sparc: Use i128 for FqTOs, FqTOi | Richard Henderson | 1 | -2/+2 |
| 2024-02-03 | target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq | Richard Henderson | 1 | -7/+5 |
| 2024-02-03 | target/sparc: Use i128 for FSQRTq | Richard Henderson | 1 | -1/+1 |
| 2024-02-03 | target/sparc: Inline FNEG, FABS | Richard Henderson | 1 | -6/+0 |
| 2023-11-05 | target/sparc: Implement UDIVX and SDIVX inline | Richard Henderson | 1 | -4/+0 |
| 2023-11-05 | target/sparc: Remove CC_OP leftovers | Richard Henderson | 1 | -2/+0 |
| 2023-11-05 | target/sparc: Remove CC_OP_DIV | Richard Henderson | 1 | -4/+2 |
| 2023-10-25 | target/sparc: Use tcg_gen_vec_{add,sub}* | Richard Henderson | 1 | -12/+0 |
| 2023-10-25 | target/sparc: Merge LDFSR, LDXFSR implementations | Richard Henderson | 1 | -2/+1 |
| 2023-10-25 | target/sparc: Implement check_align inline | Richard Henderson | 1 | -1/+0 |
| 2017-01-18 | target-sparc: implement UA2005 GL register | Artyom Tarasenko | 1 | -0/+1 |
| 2017-01-10 | target-sparc: Use ctpop helper | Richard Henderson | 1 | -1/+0 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+168 |
