riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-10-27	sh4: remove SuperHCPUClass::name field	Igor Mammedov	2	-9/+3
2017-10-27	sh4: simplify superh_cpu_class_by_name()	Igor Mammedov	1	-22/+12
2017-10-27	sh4: cleanup cpu type name composition	Igor Mammedov	3	-41/+31
2017-10-24	tcg: Initialize cpu_env generically	Richard Henderson	1	-4/+0
2017-10-24	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	1	-1/+1
2017-10-24	target/sh4: check CF_PARALLEL instead of parallel_cpus	Emilio G. Cota	1	-1/+1
2017-10-24	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	1	-3/+3
2017-10-24	qom: Introduce CPUClass.tcg_initialize	Richard Henderson	2	-11/+1
2017-10-16	linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31	Richard Henderson	1	-1/+5
2017-10-10	tcg: remove addr argument from lookup_tb_ptr	Emilio G. Cota	1	-2/+2
2017-10-09	qom/cpu: move cpu_model null check to cpu_class_by_name()	Philippe Mathieu-Daudé	1	-3/+0
2017-09-01	sh4: replace cpu_sh4_init() with cpu_generic_init()	Igor Mammedov	2	-7/+1
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+2
2017-07-18	target/sh4: Use tcg_gen_lookup_and_goto_ptr	Richard Henderson	1	-10/+20
2017-07-18	target/sh4: Implement fsrra	Richard Henderson	3	-0/+19
2017-07-18	target/sh4: Add missing FPSCR.PR == 0 checks	Richard Henderson	1	-0/+2
2017-07-18	target/sh4: Implement fpchg	Richard Henderson	1	-0/+5
2017-07-18	target/sh4: Introduce CHECK_SH4A	Richard Henderson	1	-34/+30
2017-07-18	target/sh4: Introduce CHECK_FPSCR_PR_*	Richard Henderson	1	-26/+31
2017-07-18	target/sh4: Tidy misc illegal insn checks	Richard Henderson	1	-9/+13
2017-07-18	target/sh4: Unify code for CHECK_FPU_ENABLED	Richard Henderson	1	-10/+14
2017-07-18	target/sh4: Unify code for CHECK_PRIVILEGED	Richard Henderson	1	-10/+4
2017-07-18	target/sh4: Unify code for CHECK_NOT_DELAY_SLOT	Richard Henderson	1	-6/+5
2017-07-18	target/sh4: Simplify 64-bit fp reg-reg move	Richard Henderson	1	-4/+4
2017-07-18	target/sh4: Load/store Dr as 64-bit quantities	Richard Henderson	1	-39/+36
2017-07-18	target/sh4: Merge DREG into fpr64 routines	Richard Henderson	1	-11/+15
2017-07-18	target/sh4: Eliminate unused XREG macro	Richard Henderson	1	-1/+0
2017-07-18	target/sh4: Hoist fp register bank selection	Richard Henderson	1	-3/+5
2017-07-18	target/sh4: Pass DisasContext to fpr64 routines	Richard Henderson	1	-13/+13
2017-07-18	target/sh4: Unify cpu_fregs into FREG	Richard Henderson	1	-73/+52
2017-07-18	target/sh4: Hoist register bank selection	Richard Henderson	1	-10/+11
2017-07-18	target/sh4: Recognize common gUSA sequences	Richard Henderson	1	-0/+321
2017-07-18	target/sh4: Handle user-space atomics	Richard Henderson	4	-15/+148
2017-07-18	target/sh4: Adjust TB_FLAG_PENDING_MOVCA	Richard Henderson	1	-3/+3
2017-07-18	target/sh4: Keep env->flags clean	Richard Henderson	2	-2/+2
2017-07-18	target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK	Richard Henderson	2	-3/+5
2017-07-18	target/sh4: Consolidate end-of-TB tests	Richard Henderson	1	-14/+17
2017-07-18	target/sh4: return result of fcmp using TCG	Aurelien Jarno	3	-16/+18
2017-07-18	target/sh4: do not use a helper to implement fneg	Aurelien Jarno	3	-9/+2
2017-07-18	target/sh4: fix FPSCR cause vs flag inversion	Aurelien Jarno	1	-10/+10
2017-07-18	target/sh4: fix FPU unorderered compare	Aurelien Jarno	1	-20/+8
2017-07-18	target/sh4: do not check for PR bit for fabs instruction	Aurelien Jarno	3	-24/+3
2017-05-30	target/sh4: fix RTE instruction delay slot	Aurelien Jarno	2	-5/+16
2017-05-30	target/sh4: ignore interrupts in a delay slot	Aurelien Jarno	1	-2/+10
2017-05-30	target/sh4: introduce DELAY_SLOT_MASK	Aurelien Jarno	3	-12/+12
2017-05-30	target/sh4: fix reset when using a kernel and an initrd	Aurelien Jarno	1	-1/+9
2017-05-30	target/sh4: log unauthorized accesses using qemu_log_mask	Aurelien Jarno	1	-1/+1
2017-05-13	target/sh4: use cpu_loop_exit_restore	Aurelien Jarno	1	-8/+2
2017-05-13	target/sh4: trap unaligned accesses	Aurelien Jarno	4	-2/+25
2017-05-13	target/sh4: movua.l is an SH4-A only instruction	Aurelien Jarno	1	-11/+15