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path: root/target/s390x/insn-data.def
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2021-01-21s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"David Hildenbrand1-4/+4
2021-01-21s390x/tcg: Fix ALGSIDavid Hildenbrand1-1/+1
2020-12-21target/s390x: Improve SUB LOGICAL WITH BORROWRichard Henderson1-4/+4
2020-12-21target/s390x: Improve cc computation for SUBTRACT LOGICALRichard Henderson1-12/+12
2020-12-21target/s390x: Improve ADD LOGICAL WITH CARRYRichard Henderson1-4/+4
2020-12-21target/s390x: Improve cc computation for ADD LOGICALRichard Henderson1-18/+18
2020-11-05target/s390x: fix execution with icountPavel Dovgalyuk1-35/+35
2020-10-02s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)David Hildenbrand1-0/+1
2020-10-02s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)David Hildenbrand1-0/+4
2020-10-02s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)David Hildenbrand1-0/+2
2020-10-02s390x/tcg: Implement MULTIPLY HALFWORD (MGH)David Hildenbrand1-0/+1
2020-10-02s390x/tcg: Implement MULTIPLY (MG, MGRK)David Hildenbrand1-0/+2
2020-10-02s390x/tcg: Implement SUBTRACT HALFWORD (SGH)David Hildenbrand1-0/+1
2020-10-02s390x/tcg: Implement ADD HALFWORD (AGH)David Hildenbrand1-0/+1
2020-10-02s390x/tcg: Implement MONITOR CALLDavid Hildenbrand1-0/+3
2020-07-03target/s390x: Fix SQXBRRichard Henderson1-1/+1
2020-06-02target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson1-2/+2
2019-12-18target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson1-4/+4
2019-09-23s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand1-1/+1
2019-06-07s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand1-0/+4
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand1-0/+6
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand1-0/+4
2019-06-07s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand1-0/+5
2019-06-07s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand1-0/+2
2019-06-07s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand1-0/+5
2019-05-17s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS WORDDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS QUADWORDDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORDDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATIONDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATIONDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SUBTRACTDavid Hildenbrand1-0/+2
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand1-0/+4
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