riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-10-04	s390x/tcg: handle privileged instructions via flags	David Hildenbrand	1	-69/+69
2018-10-04	s390x/tcg: add instruction flags for floating point instructions	David Hildenbrand	1	-127/+127
2018-10-04	s390x/tcg: support flags for instructions	David Hildenbrand	1	-0/+3
2018-08-28	target/s390x: add BAL and BALR instructions	Pavel Zbitskiy	1	-0/+3
2018-07-02	s390x/tcg: implement SET CLOCK	David Hildenbrand	1	-2/+1
2018-02-26	s390x/tcg: add various alignment checks	David Hildenbrand	1	-8/+8
2018-02-09	s390x/tcg: wire up pci instructions	Cornelia Huck	1	-0/+13
2018-02-09	s390x/tcg: implement TEST PENDING INTERRUPTION	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: implement extract-CPU-time facility	David Hildenbrand	1	-0/+2
2017-12-14	s390x/tcg: Implement SIGNAL ADAPTER instruction	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: Implement STORE CHANNEL PATH STATUS	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: wire up SET CHANNEL MONITOR	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: wire up SET ADDRESS LIMIT	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: implement Interlocked-Access Facility 2	David Hildenbrand	1	-6/+6
2017-12-14	s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1	David Hildenbrand	1	-4/+4
2017-12-14	s390x/tcg: wire up STORE CHANNEL REPORT WORD	David Hildenbrand	1	-0/+1
2017-12-14	s390x/tcg: implement SET CLOCK PROGRAMMABLE FIELD	David Hildenbrand	1	-0/+2
2017-10-20	s390x/tcg: switch to new SIGP handling code	David Hildenbrand	1	-1/+1
2017-10-06	s390x/tcg: add basic MSA features	David Hildenbrand	1	-0/+13
2017-10-06	s390x/tcg: implement spm (SET PROGRAM MASK)	David Hildenbrand	1	-0/+2
2017-07-17	target/s390x: Implement TRTR	Richard Henderson	1	-0/+2
2017-07-17	target/s390x: Implement SRSTU	Richard Henderson	1	-0/+2
2017-07-17	target/s390x: Tidy SRST	Richard Henderson	1	-1/+1
2017-07-17	target/s390x: Implement CONVERT UNICODE insns	Richard Henderson	1	-0/+13
2017-07-17	target/s390x: Implement CSST	Richard Henderson	1	-0/+2
2017-06-23	target/s390x: Implement idte instruction	David Hildenbrand	1	-0/+2
2017-06-23	target/s390x: Implement processor-assist insn	Richard Henderson	1	-0/+3
2017-06-23	target/s390x: Implement execution-hint insns	Richard Henderson	1	-0/+9
2017-06-23	target/s390x: Implement load-and-zero-rightmost-byte insns	Richard Henderson	1	-0/+5
2017-06-23	target/s390x: Implement load-on-condition-2 insns	Richard Henderson	1	-0/+9
2017-06-23	target/s390x: implement mvcos instruction	David Hildenbrand	1	-0/+2
2017-06-13	s390x/cpumodel: wire up cpu type + id for TCG	David Hildenbrand	1	-1/+1
2017-06-06	target/s390x: implement STORE PAIR TO QUADWORD	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement LOAD PAIR FROM QUADWORD	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement TRANSLATE ONE/TWO TO ONE/TWO	Aurelien Jarno	1	-0/+9
2017-06-06	target/s390x: implement TEST DECIMAL	Aurelien Jarno	1	-0/+3
2017-06-06	target/s390x: implement UNPACK UNICODE	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement UNPACK ASCII	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement PACK UNICODE	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement PACK ASCII	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement MOVE LONG UNICODE	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement COMPARE LOGICAL LONG UNICODE	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement COMPARE LOGICAL LONG	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement MOVE ZONES	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement MOVE WITH OFFSET	Aurelien Jarno	1	-0/+4
2017-06-06	target/s390x: implement MOVE NUMERICS	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement MOVE INVERSE	Aurelien Jarno	1	-0/+2
2017-06-06	target/s390x: implement COMPARE AND SIGNAL	Aurelien Jarno	1	-0/+6
2017-06-06	target/s390x: implement PACK	Aurelien Jarno	1	-0/+5
2017-06-06	target/s390x: implement TEST ADDRESSING MODE	Aurelien Jarno	1	-0/+3