riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-26	Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	1	-2/+7
2022-10-26	target/riscv: Convert to tcg_ops restore_state_to_opc	Richard Henderson	1	-2/+7
2022-10-24	treewide: Remove the unnecessary space before semicolon	Bin Meng	1	-1/+1
2022-10-14	target/riscv: pmp: Fixup TLB size calculation	Alistair Francis	1	-0/+12
2022-10-13	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi	1	-0/+4
2022-10-10	kvm: allow target-specific accelerator properties	Paolo Bonzini	1	-0/+4
2022-10-06	dump: Replace opaque DumpState pointer with a typed one	Janosch Frank	2	-6/+4
2022-10-04	accel/tcg: Introduce tb_pc and log_pc	Richard Henderson	1	-2/+2
2022-10-04	hw/core: Add CPUClass.get_pc	Richard Henderson	1	-0/+13
2022-09-27	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	Yang Liu	4	-15/+31
2022-09-27	target/riscv: rvv-1.0: Simplify vfwredsum code	Yang Liu	1	-46/+10
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang	2	-4/+188
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang	1	-0/+10
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang	2	-2/+70
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang	4	-3/+18
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang	1	-6/+3
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang	4	-88/+48
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang	2	-5/+12
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang	5	-67/+140
2022-09-27	target/riscv: Check the correct exception cause in vector GDB stub	Frank Chang	1	-2/+2
2022-09-27	target/riscv: Set the CPU resetvec directly	Alistair Francis	3	-15/+7
2022-09-27	target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml	Andrew Burgess	1	-30/+2
2022-09-27	target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}	Weiwei Li	1	-4/+9
2022-09-27	target/riscv: Remove sideleg and sedeleg	Rahul Pathak	1	-2/+0
2022-09-13	target/riscv: Honour -semihosting-config userspace=on and enable=on	Peter Maydell	3	-7/+6
2022-09-07	target/riscv: Update the privilege field for sscofpmf CSRs	Atish Patra	1	-30/+60
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra	2	-0/+58
2022-09-07	target/riscv: Add few cache related PMU events	Atish Patra	1	-0/+25
2022-09-07	target/riscv: Simplify counter predicate function	Atish Patra	1	-101/+9
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra	7	-11/+623
2022-09-07	target/riscv: Add vstimecmp support	Atish Patra	6	-6/+118
2022-09-07	target/riscv: Add stimecmp support	Atish Patra	8	-1/+235
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra	2	-5/+2
2022-09-07	target/riscv: Use official extension names for AIA CSRs	Anup Patel	4	-14/+26
2022-09-07	target/riscv: Add xicondops in ISA entry	Rahul Pathak	1	-0/+1
2022-09-07	target/riscv: Remove additional priv version check for mcountinhibit	Atish Patra	1	-8/+0
2022-09-07	target/riscv: Fix priority of csr related check in riscv_csrrw_check	Weiwei Li	1	-19/+25
2022-09-07	target/riscv: Add Zihintpause support	Dao Lu	4	-1/+25
2022-09-07	target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...	eopXD	1	-0/+1
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen	2	-2/+25
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen	2	-0/+14
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen	2	-0/+38
2022-09-07	target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...	Yueh-Ting (eop) Chen	1	-10/+16
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen	2	-0/+11
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen	2	-0/+8
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen	2	-0/+5
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen	2	-11/+29
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen	6	-2/+20
2022-09-07	target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V	Alexey Baturo	1	-1/+1
2022-09-07	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...	Weiwei Li	1	-13/+5