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2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson1-1/+2
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis1-9/+16
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis2-88/+92
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis1-5/+7
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis1-9/+10
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis1-10/+23
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2-0/+11
2020-12-17target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2-24/+8
2020-12-17target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis1-0/+6
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson1-2/+2
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang1-1/+2
2020-11-13hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf1-1/+1
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis3-42/+17
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis5-166/+59
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis4-51/+25
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis1-13/+17
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis3-3/+14
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang1-1/+1
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang1-0/+25
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang1-0/+47
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang3-11/+70
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang4-8/+81
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang6-74/+41
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2-12/+34
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer1-3/+3
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer1-1/+3
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer1-1/+1
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2-2/+7
2020-10-05icount: rename functions to be consistent with the module nameClaudio Fontana1-2/+2
2020-10-05cpu-timers, icount: new modulesClaudio Fontana1-2/+2
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-1/+1
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost1-1/+1
2020-09-18target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson1-0/+1
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell4-12/+27
2020-09-11Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell1-10/+7
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng3-5/+9
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-5/+2
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2-0/+2
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang3-2/+14
2020-09-09trace-events: Fix attribution of trace points to sourceMarkus Armbruster1-1/+1
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost1-4/+2
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-6/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-4/+7
2020-08-28softfloat: Implement the full set of comparisons for float16Kito Cheng1-25/+0
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis5-6/+109
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis2-29/+35
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2-0/+43
2020-08-25target/riscv: Only support little endian guestsAlistair Francis1-0/+5
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis1-0/+9
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis1-6/+8
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