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2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel2-70/+66
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2-168/+6
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel1-1/+1
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel1-4/+8
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis1-1/+1
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis1-1/+1
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra6-53/+213
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra3-152/+331
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra4-0/+32
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra3-36/+63
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra3-5/+5
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra1-0/+51
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra1-4/+7
2022-07-03target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre1-0/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson4-9/+17
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson1-9/+2
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson1-0/+2
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2
2022-06-28semihosting: Split out common-semi-target.hRichard Henderson1-0/+50
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson1-1/+1
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis1-2/+10
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis1-11/+46
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD1-0/+2
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD2-2/+45
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD2-0/+36
2022-06-10target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD1-0/+20
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD2-196/+261
2022-06-10target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD1-106/+114
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD2-4/+28
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD1-0/+18
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD2-1/+13
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD3-142/+190
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD3-0/+68
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD6-132/+178
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD1-0/+27
2022-06-10target/riscv: rvv: Rename ambiguous eszeopXD1-38/+38
2022-06-10target/riscv: rvv: Prune redundant access_type parameter passedeopXD1-19/+16
2022-06-10target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD1-567/+565
2022-06-10target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker3-2/+3
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li3-6/+20
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng1-0/+2
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel4-5/+23
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel1-2/+1
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel1-2/+6
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang3-7/+7
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li1-12/+12
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI1-15/+16
2022-05-24target/riscv: FP extension requirementsTsukasa OI1-0/+25
2022-05-24target/riscv: Change "G" expansionTsukasa OI1-2/+5
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