Age | Commit message (Expand) | Author | Files | Lines |
2023-09-11 | target/riscv: don't read CSR in riscv_csrrw_do64 | Nikita Shubin | 1 | -9/+15 |
2023-09-11 | target/riscv: Align the AIA model to v1.0 ratified spec | Tommy Wu | 1 | -2/+5 |
2023-09-11 | target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes | Leon Schuermann | 1 | -0/+4 |
2023-09-11 | target/riscv: Allocate itrigger timers only once | Akihiko Odaki | 3 | -5/+21 |
2023-09-11 | target/riscv: Use accelerated helper for AES64KS1I | Ard Biesheuvel | 1 | -12/+5 |
2023-09-11 | hw/intc/riscv_aplic.c fix non-KVM --enable-debug build | Daniel Henrique Barboza | 2 | -0/+6 |
2023-09-11 | riscv: zicond: make non-experimental | Vineet Gupta | 1 | -1/+1 |
2023-09-11 | target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 | Daniel Henrique Barboza | 1 | -3/+20 |
2023-09-11 | target/riscv: Update CSR bits name for svadu extension | Weiwei Li | 4 | -15/+15 |
2023-09-11 | target/riscv: Create an KVM AIA irqchip | Yong-Xuan Wang | 2 | -0/+190 |
2023-09-11 | target/riscv: check the in-kernel irqchip support | Yong-Xuan Wang | 1 | -1/+9 |
2023-09-11 | target/riscv: Fix zfa fleq.d and fltq.d | LIU Zhiwei | 1 | -2/+2 |
2023-09-11 | target/riscv: Add Zihintntl extension ISA string to DTS | Jason Chien | 2 | -0/+3 |
2023-09-11 | target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren | Rob Bradford | 1 | -2/+9 |
2023-09-11 | target/riscv: Add Zvksed ISA extension support | Max Chou | 6 | -1/+184 |
2023-09-11 | target/riscv: Add Zvkg ISA extension support | Nazar Kazakov | 6 | -2/+114 |
2023-09-11 | target/riscv: Add Zvksh ISA extension support | Lawrence Hunter | 6 | -2/+177 |
2023-09-11 | target/riscv: Add Zvknh ISA extension support | Kiran Ostrolenk | 6 | -3/+390 |
2023-09-11 | target/riscv: Add Zvkned ISA extension support | Nazar Kazakov | 6 | -1/+381 |
2023-09-11 | target/riscv: Add Zvbb ISA extension support | Dickon Hood | 6 | -0/+397 |
2023-09-11 | target/riscv: Refactor some of the generic vector functionality | Kiran Ostrolenk | 2 | -42/+46 |
2023-09-11 | target/riscv: Refactor translation of vector-widening instruction | Dickon Hood | 1 | -29/+23 |
2023-09-11 | target/riscv: Move vector translation checks | Nazar Kazakov | 1 | -16/+12 |
2023-09-11 | target/riscv: Add Zvbc ISA extension support | Lawrence Hunter | 8 | -1/+146 |
2023-09-11 | target/riscv: Remove redundant "cpu_vl == 0" checks | Nazar Kazakov | 1 | -30/+1 |
2023-09-11 | target/riscv: Refactor vector-vector translation macro | Kiran Ostrolenk | 1 | -30/+32 |
2023-09-11 | target/riscv: Refactor some of the generic vector functionality | Kiran Ostrolenk | 4 | -200/+265 |
2023-09-11 | target/riscv: Use existing lookup tables for MixColumns | Ard Biesheuvel | 1 | -30/+4 |
2023-09-11 | target/riscv: Fix page_check_range use in fault-only-first | LIU Zhiwei | 1 | -1/+1 |
2023-09-11 | target/riscv/cpu.c: add smepmp isa string | Daniel Henrique Barboza | 1 | -0/+1 |
2023-09-11 | target/riscv/cpu.c: add zmmul isa string | Daniel Henrique Barboza | 1 | -0/+1 |
2023-09-11 | target/riscv/cpu.c: do not run 'host' CPU with TCG | Daniel Henrique Barboza | 1 | -0/+5 |
2023-09-08 | riscv: spelling fixes | Michael Tokarev | 8 | -17/+17 |
2023-08-31 | target/helpers: Remove unnecessary 'qemu/main-loop.h' header | Philippe Mathieu-Daudé | 4 | -4/+0 |
2023-08-31 | target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header | Philippe Mathieu-Daudé | 1 | -1/+0 |
2023-08-31 | target/translate: Include missing 'exec/cpu_ldst.h' header | Philippe Mathieu-Daudé | 2 | -0/+2 |
2023-08-31 | target/riscv/pmu: Restrict 'qemu/log.h' include to source | Philippe Mathieu-Daudé | 2 | -1/+1 |
2023-08-24 | include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*() | Anton Johansson | 1 | -1/+1 |
2023-08-22 | kvm: Introduce kvm_arch_get_default_type hook | Akihiko Odaki | 1 | -0/+5 |
2023-08-11 | target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() | Daniel Henrique Barboza | 1 | -1/+8 |
2023-07-19 | target/riscv: Fix LMUL check to use VLEN | Rob Bradford | 1 | -2/+2 |
2023-07-19 | target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf | Daniel Henrique Barboza | 1 | -1/+2 |
2023-07-15 | accel/tcg: Return bool from page_check_range | Richard Henderson | 1 | -1/+1 |
2023-07-10 | riscv: Add support for the Zfa extension | Christoph Müllner | 7 | -0/+730 |
2023-07-10 | target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM | Daniel Henrique Barboza | 1 | -0/+70 |
2023-07-10 | target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper | Daniel Henrique Barboza | 1 | -4/+7 |
2023-07-10 | target/riscv: update multi-letter extension KVM properties | Daniel Henrique Barboza | 1 | -0/+27 |
2023-07-10 | target/riscv/cpu.c: create KVM mock properties | Daniel Henrique Barboza | 1 | -0/+36 |
2023-07-10 | target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() | Daniel Henrique Barboza | 1 | -2/+1 |
2023-07-10 | target/riscv/cpu.c: add satp_mode properties earlier | Daniel Henrique Barboza | 1 | -4/+2 |