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Author
Files
Lines
2021-07-21
accel/tcg: Remove TranslatorOps.breakpoint_check
Richard Henderson
1
-17
/
+0
2021-07-15
target/riscv: hardwire bits in hideleg and hedeleg
Jose Martins
1
-23
/
+31
2021-07-15
target/riscv: csr: Remove redundant check in fp csr read/write routines
Bin Meng
1
-24
/
+0
2021-07-15
target/riscv: pmp: Fix some typos
Bin Meng
1
-5
/
+5
2021-07-12
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...
Peter Maydell
1
-19
/
+1
2021-07-09
target/riscv: Use translator_use_goto_tb
Richard Henderson
1
-19
/
+1
2021-07-09
meson: Introduce target-specific Kconfig
Philippe Mathieu-Daudé
1
-0
/
+5
2021-06-24
target/riscv: gdbstub: Fix dynamic CSR XML generation
Bin Meng
1
-1
/
+1
2021-06-24
target/riscv: Use target_ulong for the DisasContext misa
Alistair Francis
1
-1
/
+1
2021-06-08
target/riscv: rvb: add b-ext version cpu option
Frank Chang
2
-0
/
+26
2021-06-08
target/riscv: rvb: support and turn on B-extension from command line
Kito Cheng
2
-0
/
+5
2021-06-08
target/riscv: rvb: add/shift with prefix zero-extend
Kito Cheng
3
-0
/
+35
2021-06-08
target/riscv: rvb: address calculation
Kito Cheng
3
-0
/
+62
2021-06-08
target/riscv: rvb: generalized or-combine
Frank Chang
5
-0
/
+64
2021-06-08
target/riscv: rvb: generalized reverse
Frank Chang
6
-0
/
+132
2021-06-08
target/riscv: rvb: rotate (left/right)
Kito Cheng
3
-0
/
+81
2021-06-08
target/riscv: rvb: shift ones
Kito Cheng
3
-0
/
+74
2021-06-08
target/riscv: rvb: single-bit instructions
Frank Chang
3
-0
/
+175
2021-06-08
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
Frank Chang
2
-50
/
+43
2021-06-08
target/riscv: rvb: sign-extend instructions
Kito Cheng
2
-0
/
+15
2021-06-08
target/riscv: rvb: min/max instructions
Kito Cheng
2
-0
/
+28
2021-06-08
target/riscv: rvb: pack two words into one register
Kito Cheng
3
-0
/
+78
2021-06-08
target/riscv: rvb: logic-with-negate
Kito Cheng
2
-0
/
+21
2021-06-08
target/riscv: rvb: count bits set
Frank Chang
3
-0
/
+21
2021-06-08
target/riscv: rvb: count leading/trailing zeros
Kito Cheng
4
-1
/
+93
2021-06-08
target/riscv: reformat @sh format encoding for B-extension
Kito Cheng
1
-5
/
+5
2021-06-08
target/riscv: Pass the same value to oprsz and maxsz.
LIU Zhiwei
1
-39
/
+50
2021-06-08
target/riscv/pmp: Add assert for ePMP operations
Alistair Francis
1
-0
/
+4
2021-06-08
target/riscv: Dump CSR mscratch/sscratch/satp
Changbin Du
1
-2
/
+5
2021-06-08
target/riscv: Remove unnecessary riscv_*_names[] declaration
Bin Meng
2
-4
/
+2
2021-06-08
target/riscv: Do not include 'pmp.h' in user emulation
Philippe Mathieu-Daudé
1
-0
/
+2
2021-06-08
target/riscv: fix wfi exception behavior
Jose Martins
2
-3
/
+9
2021-05-26
hw/core: Constify TCGCPUOps
Richard Henderson
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Move CPUClass::write_elf* to SysemuCPUOps
Philippe Mathieu-Daudé
1
-2
/
+2
2021-05-26
cpu: Move CPUClass::vmsd to SysemuCPUOps
Philippe Mathieu-Daudé
1
-1
/
+1
2021-05-26
cpu: Introduce SysemuCPUOps structure
Philippe Mathieu-Daudé
1
-0
/
+8
2021-05-26
cpu: Rename CPUClass vmsd -> legacy_vmsd
Philippe Mathieu-Daudé
1
-2
/
+1
2021-05-11
target/riscv: Fix the RV64H decode comment
Alistair Francis
1
-1
/
+1
2021-05-11
target/riscv: Consolidate RV32/64 16-bit instructions
Alistair Francis
5
-72
/
+39
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
14
-150
/
+166
2021-05-11
target/riscv: Remove an unused CASE_OP_32_64 macro
Alistair Francis
1
-6
/
+0
2021-05-11
target/riscv: Remove the unused HSTATUS_WPRI macro
Alistair Francis
1
-6
/
+0
2021-05-11
target/riscv: Remove the hardcoded SATP_MODE macro
Alistair Francis
4
-28
/
+56
2021-05-11
target/riscv: Remove the hardcoded MSTATUS_SD macro
Alistair Francis
3
-14
/
+27
2021-05-11
target/riscv: Remove the hardcoded HGATP_MODE macro
Alistair Francis
2
-20
/
+15
2021-05-11
target/riscv: Remove the hardcoded SSTATUS_SD macro
Alistair Francis
2
-7
/
+8
2021-05-11
target/riscv: Remove the hardcoded RVXLEN macro
Alistair Francis
2
-7
/
+5
2021-05-11
target/riscv: fix a typo with interrupt names
Emmanuel Blot
1
-1
/
+1
2021-05-11
target/riscv: fix exception index on instruction access fault
Emmanuel Blot
1
-1
/
+3
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