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2024-01-31Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingPeter Maydell2-1/+1
2024-01-30riscv: Clean up includesPeter Maydell2-1/+1
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-1/+1
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson1-1/+1
2024-01-19target/riscv: Rename tcg_cpu_FOO() to include 'riscv'Philippe Mathieu-Daudé1-14/+14
2024-01-10target/riscv: Ensure mideleg is set correctly on resetAlistair Francis1-0/+8
2024-01-10target/riscv: Don't adjust vscause for exceptionsAlistair Francis1-2/+2
2024-01-10target/riscv: Assert that the CSR numbers will be correctAlistair Francis1-1/+4
2024-01-10target/riscv: pmp: Ignore writes when RW=01 and MML=0Ivan Klokov1-1/+1
2024-01-10target/riscv/kvm: add RVV and Vector CSR regsDaniel Henrique Barboza1-0/+74
2024-01-10target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()Daniel Henrique Barboza1-0/+29
2024-01-10target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...Yong-Xuan Wang1-14/+17
2024-01-10target/riscv: add rva22s64 cpuDaniel Henrique Barboza2-0/+9
2024-01-10target/riscv: add RVA22S64 profileDaniel Henrique Barboza1-0/+32
2024-01-10target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza3-1/+15
2024-01-10target/riscv: add satp_mode profile supportDaniel Henrique Barboza3-0/+42
2024-01-10target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza2-1/+7
2024-01-10target/riscv/cpu.c: finalize satp_mode earlierDaniel Henrique Barboza1-8/+8
2024-01-10target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza3-0/+34
2024-01-10target/riscv: implement svadeDaniel Henrique Barboza3-0/+7
2024-01-10target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza3-0/+27
2024-01-10riscv-qmp-cmds.c: add profile flags in cpu-model-expansionDaniel Henrique Barboza1-0/+14
2024-01-10target/riscv/tcg: validate profiles during finalizeDaniel Henrique Barboza1-0/+69
2024-01-10target/riscv/tcg: honor user choice for G MISA bitsDaniel Henrique Barboza1-25/+48
2024-01-10target/riscv/tcg: add hash table insert helpersDaniel Henrique Barboza1-12/+16
2024-01-10target/riscv/tcg: handle profile MISA bitsDaniel Henrique Barboza1-0/+21
2024-01-10target/riscv/tcg: add riscv_cpu_write_misa_bit()Daniel Henrique Barboza1-14/+18
2024-01-10target/riscv/tcg: add MISA user options hashDaniel Henrique Barboza1-1/+14
2024-01-10target/riscv/tcg: add user flag for profile supportDaniel Henrique Barboza1-0/+80
2024-01-10target/riscv/kvm: add 'rva22u64' flag as unavailableDaniel Henrique Barboza1-1/+6
2024-01-10target/riscv: add rva22u64 profile definitionDaniel Henrique Barboza2-0/+44
2024-01-10riscv-qmp-cmds.c: expose named features in cpu_model_expansionDaniel Henrique Barboza1-5/+25
2024-01-10target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza4-0/+34
2024-01-10target/riscv: add zicbop extension flagDaniel Henrique Barboza2-0/+5
2024-01-10target/riscv: add rv64i CPUDaniel Henrique Barboza2-0/+48
2024-01-10target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza1-0/+32
2024-01-10target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza1-4/+9
2024-01-10target/riscv: create TYPE_RISCV_VENDOR_CPUDaniel Henrique Barboza2-9/+22
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li6-0/+165
2024-01-10target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()Daniel Henrique Barboza1-19/+21
2024-01-10target/riscv/kvm: add RISCV_CONFIG_REG()Daniel Henrique Barboza1-14/+11
2024-01-10target/riscv/kvm: change timer regs size to u64Daniel Henrique Barboza1-13/+13
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64Daniel Henrique Barboza1-3/+8
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32Daniel Henrique Barboza1-3/+8
2024-01-10target/riscv/cpu.c: fix machine IDs gettersDaniel Henrique Barboza1-6/+6
2024-01-10target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov2-18/+16
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei1-1/+4
2024-01-10target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei1-1/+1
2024-01-10target/riscv: The whole vector register move instructions depend on vsewMax Chou1-2/+1
2024-01-10target/riscv: Add vill check for whole vector register move instructionsMax Chou1-2/+3
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