index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2024-02-03
include/exec: Implement cpu_mmu_index generically
Richard Henderson
1
-2
/
+0
2024-02-03
target/riscv: Populate CPUClass.mmu_index
Richard Henderson
1
-0
/
+6
2024-02-03
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
Richard Henderson
3
-8
/
+9
2024-02-03
target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index
Richard Henderson
2
-3
/
+3
2024-01-31
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
Peter Maydell
2
-1
/
+1
2024-01-30
riscv: Clean up includes
Peter Maydell
2
-1
/
+1
2024-01-29
include/qemu: Add TCGCPUOps typedef to typedefs.h
Richard Henderson
1
-1
/
+1
2024-01-29
target: Use vaddr in gen_intermediate_code
Anton Johansson
1
-1
/
+1
2024-01-19
target/riscv: Rename tcg_cpu_FOO() to include 'riscv'
Philippe Mathieu-Daudé
1
-14
/
+14
2024-01-10
target/riscv: Ensure mideleg is set correctly on reset
Alistair Francis
1
-0
/
+8
2024-01-10
target/riscv: Don't adjust vscause for exceptions
Alistair Francis
1
-2
/
+2
2024-01-10
target/riscv: Assert that the CSR numbers will be correct
Alistair Francis
1
-1
/
+4
2024-01-10
target/riscv: pmp: Ignore writes when RW=01 and MML=0
Ivan Klokov
1
-1
/
+1
2024-01-10
target/riscv/kvm: add RVV and Vector CSR regs
Daniel Henrique Barboza
1
-0
/
+74
2024-01-10
target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
Daniel Henrique Barboza
1
-0
/
+29
2024-01-10
target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...
Yong-Xuan Wang
1
-14
/
+17
2024-01-10
target/riscv: add rva22s64 cpu
Daniel Henrique Barboza
2
-0
/
+9
2024-01-10
target/riscv: add RVA22S64 profile
Daniel Henrique Barboza
1
-0
/
+32
2024-01-10
target/riscv: add 'parent' in profile description
Daniel Henrique Barboza
3
-1
/
+15
2024-01-10
target/riscv: add satp_mode profile support
Daniel Henrique Barboza
3
-0
/
+42
2024-01-10
target/riscv/cpu.c: add riscv_cpu_is_32bit()
Daniel Henrique Barboza
2
-1
/
+7
2024-01-10
target/riscv/cpu.c: finalize satp_mode earlier
Daniel Henrique Barboza
1
-8
/
+8
2024-01-10
target/riscv: add priv ver restriction to profiles
Daniel Henrique Barboza
3
-0
/
+34
2024-01-10
target/riscv: implement svade
Daniel Henrique Barboza
3
-0
/
+7
2024-01-10
target/riscv: add 'rva22u64' CPU
Daniel Henrique Barboza
3
-0
/
+27
2024-01-10
riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
Daniel Henrique Barboza
1
-0
/
+14
2024-01-10
target/riscv/tcg: validate profiles during finalize
Daniel Henrique Barboza
1
-0
/
+69
2024-01-10
target/riscv/tcg: honor user choice for G MISA bits
Daniel Henrique Barboza
1
-25
/
+48
2024-01-10
target/riscv/tcg: add hash table insert helpers
Daniel Henrique Barboza
1
-12
/
+16
2024-01-10
target/riscv/tcg: handle profile MISA bits
Daniel Henrique Barboza
1
-0
/
+21
2024-01-10
target/riscv/tcg: add riscv_cpu_write_misa_bit()
Daniel Henrique Barboza
1
-14
/
+18
2024-01-10
target/riscv/tcg: add MISA user options hash
Daniel Henrique Barboza
1
-1
/
+14
2024-01-10
target/riscv/tcg: add user flag for profile support
Daniel Henrique Barboza
1
-0
/
+80
2024-01-10
target/riscv/kvm: add 'rva22u64' flag as unavailable
Daniel Henrique Barboza
1
-1
/
+6
2024-01-10
target/riscv: add rva22u64 profile definition
Daniel Henrique Barboza
2
-0
/
+44
2024-01-10
riscv-qmp-cmds.c: expose named features in cpu_model_expansion
Daniel Henrique Barboza
1
-5
/
+25
2024-01-10
target/riscv/tcg: add 'zic64b' support
Daniel Henrique Barboza
4
-0
/
+34
2024-01-10
target/riscv: add zicbop extension flag
Daniel Henrique Barboza
2
-0
/
+5
2024-01-10
target/riscv: add rv64i CPU
Daniel Henrique Barboza
2
-0
/
+48
2024-01-10
target/riscv/tcg: update priv_ver on user_set extensions
Daniel Henrique Barboza
1
-0
/
+32
2024-01-10
target/riscv/tcg: do not use "!generic" CPU checks
Daniel Henrique Barboza
1
-4
/
+9
2024-01-10
target/riscv: create TYPE_RISCV_VENDOR_CPU
Daniel Henrique Barboza
2
-9
/
+22
2024-01-10
target/riscv: Add support for Zacas extension
Weiwei Li
6
-0
/
+165
2024-01-10
target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()
Daniel Henrique Barboza
1
-19
/
+21
2024-01-10
target/riscv/kvm: add RISCV_CONFIG_REG()
Daniel Henrique Barboza
1
-14
/
+11
2024-01-10
target/riscv/kvm: change timer regs size to u64
Daniel Henrique Barboza
1
-13
/
+13
2024-01-10
target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64
Daniel Henrique Barboza
1
-3
/
+8
2024-01-10
target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
Daniel Henrique Barboza
1
-3
/
+8
2024-01-10
target/riscv/cpu.c: fix machine IDs getters
Daniel Henrique Barboza
1
-6
/
+6
2024-01-10
target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
Ivan Klokov
2
-18
/
+16
[next]