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AgeCommit message (Expand)AuthorFilesLines
2024-07-18target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSRYu-Ming Chang3-9/+58
2024-07-18target/riscv: Expose the Smcntrpmf configAtish Patra1-0/+1
2024-07-18target/riscv: Do not setup pmu timer if OF is disabledAtish Patra1-12/+44
2024-07-18target/riscv: More accurately model priv mode filtering.Rajnesh Kanwal3-4/+33
2024-07-18target/riscv: Start counters from both mhpmcounter and mcountinhibitRajnesh Kanwal2-24/+54
2024-07-18target/riscv: Enforce WARL behavior for scounteren/hcounterenAtish Patra1-2/+10
2024-07-18target/riscv: Save counter values during countinhibit updateAtish Patra3-16/+24
2024-07-18target/riscv: Implement privilege mode filtering for cycle/instretAtish Patra5-37/+194
2024-07-18target/riscv: Only set INH fields if priv mode is availableAtish Patra1-4/+25
2024-07-18target/riscv: Add cycle & instret privilege mode filtering supportKaiwen Xue2-1/+149
2024-07-18target/riscv: Add cycle & instret privilege mode filtering definitionsKaiwen Xue2-0/+35
2024-07-18target/riscv: Add cycle & instret privilege mode filtering propertiesKaiwen Xue2-0/+2
2024-07-18target/riscv: Fix the predicate functions for mhpmeventhX CSRsAtish Patra1-29/+38
2024-07-18target/riscv: Combine set_mode and set_virt functions.Rajnesh Kanwal3-41/+35
2024-07-18target/riscv/kvm: update KVM regs to Linux 6.10-rc5Daniel Henrique Barboza1-0/+2
2024-07-18target/riscv: Validate the mode in write_vstvecJiayi Li1-1/+6
2024-07-18target/riscv: Expose zabha extension as a cpu propertyLIU Zhiwei1-0/+2
2024-07-18target/riscv: Add amocas.[b|h] for ZabhaLIU Zhiwei2-0/+16
2024-07-18target/riscv: Move gen_cmpxchg before adding amocas.[b|h]LIU Zhiwei2-13/+13
2024-07-18target/riscv: Add AMO instructions for ZabhaLIU Zhiwei4-1/+155
2024-07-18target/riscv: Move gen_amo before implement ZabhaLIU Zhiwei2-21/+21
2024-07-18target/riscv: Support Zama16b extensionLIU Zhiwei6-22/+57
2024-07-18target/riscv: Add zcmop extensionLIU Zhiwei6-0/+39
2024-07-18target/riscv: Add zimop extensionLIU Zhiwei5-0/+52
2024-07-11target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementationPeter Maydell3-1/+6
2024-06-27target/riscv: Apply modularized matching conditions for icount triggerAlvin Chang1-1/+1
2024-06-27target/riscv: Apply modularized matching conditions for watchpointAlvin Chang1-20/+6
2024-06-27target/riscv: Add functions for common matching conditions of triggerAlvin Chang1-23/+78
2024-06-26target/riscv: Remove extension auto-update check statementsFrank Chang1-119/+0
2024-06-26target/riscv: Add Zc extension implied ruleFrank Chang1-0/+34
2024-06-26target/riscv: Add multi extension implied rulesFrank Chang1-0/+340
2024-06-26target/riscv: Add MISA extension implied rulesFrank Chang1-1/+49
2024-06-26target/riscv: Introduce extension implied rule helpersFrank Chang1-0/+121
2024-06-26target/riscv: Introduce extension implied rules definitionFrank Chang2-0/+31
2024-06-26target/riscv: fix instructions count handling in icount modeClément Léger1-13/+17
2024-06-26target/riscv: Fix froundnx.h nanbox checkBranislav Brzak1-1/+1
2024-06-26target/riscv: Support the version for ss1p13Fea.Wang2-1/+9
2024-06-26target/riscv: Reserve exception codes for sw-check and hw-errFea.Wang1-0/+2
2024-06-26target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang2-0/+33
2024-06-26target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang2-0/+9
2024-06-26target/riscv: Define macros and variables for ss1p13Fea.Wang2-1/+4
2024-06-26target/riscv: Reuse the conversion function of priv_specJim Shu3-10/+6
2024-06-26target/riscv/kvm: handle the exit with debug reasonChao Du1-0/+20
2024-06-26target/riscv/kvm: add software breakpoints supportChao Du1-0/+69
2024-06-26target/riscv: zvbb implies zvkbJerry Zhang Jian1-0/+4
2024-06-26target/riscv: Move Guest irqs out of the core local irqs range.Rajnesh Kanwal2-2/+10
2024-06-26target/riscv: Extend virtual irq csrs masks to be 64 bit wide.Rajnesh Kanwal1-7/+7
2024-06-04Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into sta...Richard Henderson4-10/+13
2024-06-04target/riscv: Restrict riscv_cpu_do_interrupt() to sysemuPhilippe Mathieu-Daudé2-7/+5
2024-06-04target/riscv: Restrict 'rv128' machine to TCG acceleratorPhilippe Mathieu-Daudé1-2/+8
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