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AgeCommit message (Expand)AuthorFilesLines
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé1-2/+4
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-10/+10
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell1-1/+1
2018-05-18target/riscv: Honor CPU_DUMP_FPURichard Henderson1-5/+7
2018-05-17target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-4/+2
2018-05-11Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell1-49/+17
2018-05-10target/riscv: Use new atomic min/max expandersRichard Henderson1-49/+17
2018-05-09target/riscv: convert to TranslatorOpsEmilio G. Cota1-78/+80
2018-05-09target/riscv: convert to DisasContextBaseEmilio G. Cota1-65/+64
2018-05-09target/riscv: convert to DisasJumpTypeEmilio G. Cota1-44/+28
2018-05-09target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota1-3/+3
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark1-12/+13
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark1-6/+8
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark2-2/+28
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark2-18/+50
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark1-2/+5
2018-05-06RISC-V: Clear mtval/stval on exceptions without infoMichael Clark1-0/+8
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark1-2/+5
2018-05-06RISC-V: Update E and I extension orderMichael Clark2-1/+2
2018-05-06RISC-V: Remove erroneous comment from translate.cMichael Clark1-1/+0
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark1-1/+0
2018-03-29RISC-V: Workaround for critical mstatus.FS bugMichael Clark1-2/+15
2018-03-28RISC-V: Convert cpu definition to future modelMichael Clark1-54/+69
2018-03-20Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell1-0/+1
2018-03-20RISC-V: Fix riscv_isa_string memory size bugMichael Clark1-6/+6
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-03-07RISC-V Build InfrastructureMichael Clark1-0/+1
2018-03-07RISC-V Linux User EmulationMichael Clark1-0/+13
2018-03-07RISC-V Physical Memory ProtectionMichael Clark2-0/+444
2018-03-07RISC-V TCG Code GenerationMichael Clark2-0/+2342
2018-03-07RISC-V GDB StubMichael Clark1-0/+62
2018-03-07RISC-V FPU SupportMichael Clark1-0/+373
2018-03-07RISC-V CPU HelpersMichael Clark3-0/+1250
2018-03-07RISC-V CPU Core DefinitionMichael Clark3-0/+1139