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AgeCommit message (Expand)AuthorFilesLines
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson10-215/+1
2023-03-05target/riscv: Drop temp_newRichard Henderson2-25/+7
2023-03-05target/riscv: Drop ftemp_newRichard Henderson1-20/+4
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell17-542/+504
2023-03-01Merge patch series "target/riscv: some vector_helper.c cleanups"Palmer Dabbelt1-65/+39
2023-03-01target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfigDaniel Henrique Barboza1-10/+10
2023-03-01target/riscv/vector_helper.c: create vext_set_tail_elems_1s()Daniel Henrique Barboza1-56/+30
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt1-61/+48
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza1-23/+9
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza1-38/+12
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza1-3/+2
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza1-2/+1
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt5-8/+47
2023-03-01target/riscv: Export Svadu propertyWeiwei Li1-0/+3
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li2-2/+10
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li2-2/+11
2023-03-01target/riscv: Add csr support for svaduWeiwei Li3-6/+16
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...Weiwei Li1-4/+9
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...Weiwei Li1-2/+6
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li5-0/+57
2023-03-01RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner1-4/+0
2023-03-01target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song1-1/+1
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt2-240/+201
2023-03-01target/riscv: Group all predicate() routines togetherBin Meng1-90/+87
2023-03-01target/riscv: Drop priv level check in mseccfg predicate()Bin Meng1-1/+1
2023-03-01target/riscv: Allow debugger to access sstc CSRsBin Meng1-5/+14
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng1-2/+20
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng1-0/+4
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng1-0/+4
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng1-75/+0
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng1-0/+9
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng1-15/+9
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng1-24/+12
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng1-2/+2
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng1-1/+1
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng1-30/+32
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng1-3/+6
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng1-2/+2
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng1-5/+1
2023-03-01target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...Bin Meng1-1/+10
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng1-0/+3
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt6-170/+146
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li1-0/+7
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li1-8/+4
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li1-5/+4
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li1-2/+29
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li1-107/+21
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li1-4/+4
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li3-9/+4
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li1-22/+22
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