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AgeCommit message (Expand)AuthorFilesLines
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé1-3/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-3/+2
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé1-0/+2
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé1-0/+1
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li1-0/+5
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li4-143/+296
2022-03-03target/riscv: add support for zdinxWeiwei Li2-78/+259
2022-03-03target/riscv: add support for zfinxWeiwei Li5-145/+369
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li3-6/+29
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li2-0/+16
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich1-4/+4
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé1-0/+1
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li3-1/+6
2022-02-16target/riscv: add support for svinval extensionWeiwei Li5-0/+85
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li3-3/+18
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li1-0/+3
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren3-1/+30
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel2-0/+6
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel1-0/+203
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel3-0/+187
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel1-0/+156
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel1-0/+23
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel3-1/+131
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel4-120/+474
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel4-21/+294
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2-0/+37
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel1-0/+119
2022-02-16target/riscv: Add AIA cpu featureAnup Patel1-1/+2
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel2-8/+8
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel1-0/+13
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel6-38/+121
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel3-8/+16
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel1-1/+1
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei1-0/+1
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich6-0/+83
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich1-5/+27
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich1-4/+4
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich4-69/+97
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich1-0/+2
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich1-37/+41
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot2-2/+4
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei2-6/+25
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei1-0/+10
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei1-1/+0
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2-2/+10
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