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AgeCommit message (Expand)AuthorFilesLines
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson1-18/+20
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson1-15/+10
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson1-2/+12
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson3-202/+125
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson2-23/+15
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson2-233/+234
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson2-127/+127
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson1-22/+18
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson2-50/+8
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson4-90/+64
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson1-16/+81
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson9-144/+144
2021-09-01target/riscv: Clean up division helpersRichard Henderson1-83/+91
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson3-70/+34
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei1-3/+5
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei1-6/+8
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng1-1/+1
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-17/+0
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins1-23/+31
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng1-24/+0
2021-07-15target/riscv: pmp: Fix some typosBin Meng1-5/+5
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell1-19/+1
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson1-19/+1
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé1-0/+5
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng1-1/+1
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang2-0/+26
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2-0/+5
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng3-0/+35
2021-06-08target/riscv: rvb: address calculationKito Cheng3-0/+62
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang5-0/+64
2021-06-08target/riscv: rvb: generalized reverseFrank Chang6-0/+132
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng3-0/+81
2021-06-08target/riscv: rvb: shift onesKito Cheng3-0/+74
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang3-0/+175
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2-50/+43
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng2-0/+15
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng2-0/+28
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng3-0/+78
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng2-0/+21
2021-06-08target/riscv: rvb: count bits setFrank Chang3-0/+21
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng4-1/+93
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
2021-06-08target/riscv/pmp: Add assert for ePMP operationsAlistair Francis1-0/+4
2021-06-08target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du1-2/+5
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2-4/+2
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-06-08target/riscv: fix wfi exception behaviorJose Martins2-3/+9
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
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