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AgeCommit message (Expand)AuthorFilesLines
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé4-4/+0
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2-0/+2
2023-08-31target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé2-1/+1
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson1-1/+1
2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki1-0/+5
2023-08-11target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()Daniel Henrique Barboza1-1/+8
2023-07-19target/riscv: Fix LMUL check to use VLENRob Bradford1-2/+2
2023-07-19target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcfDaniel Henrique Barboza1-1/+2
2023-07-15accel/tcg: Return bool from page_check_rangeRichard Henderson1-1/+1
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner7-0/+730
2023-07-10target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVMDaniel Henrique Barboza1-0/+70
2023-07-10target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helperDaniel Henrique Barboza1-4/+7
2023-07-10target/riscv: update multi-letter extension KVM propertiesDaniel Henrique Barboza1-0/+27
2023-07-10target/riscv/cpu.c: create KVM mock propertiesDaniel Henrique Barboza1-0/+36
2023-07-10target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()Daniel Henrique Barboza1-2/+1
2023-07-10target/riscv/cpu.c: add satp_mode properties earlierDaniel Henrique Barboza1-4/+2
2023-07-10target/riscv/kvm.c: add multi-letter extension KVM propertiesDaniel Henrique Barboza2-0/+127
2023-07-10target/riscv/kvm.c: update KVM MISA bitsDaniel Henrique Barboza1-0/+40
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza2-0/+83
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza2-29/+88
2023-07-10target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPUDaniel Henrique Barboza1-11/+23
2023-07-10target/riscv: handle mvendorid/marchid/mimpid for KVM CPUsDaniel Henrique Barboza1-0/+31
2023-07-10target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()Daniel Henrique Barboza1-0/+16
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza3-0/+92
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza1-7/+53
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza1-2/+32
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza1-1/+37
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza1-10/+25
2023-07-10target/riscv KVM_RISCV_SET_TIMER macro is not configured correctlyyang.zhang1-1/+1
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien1-1/+0
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li1-0/+7
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li4-0/+76
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li4-0/+77
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li6-6/+80
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li2-0/+23
2023-07-10target/riscv: Add RVV registers to logIvan Klokov1-1/+56
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li2-9/+25
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li3-8/+55
2023-07-10target/riscv/cpu.c: fix veyron-v1 CPU propertiesDaniel Henrique Barboza1-0/+3
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li1-4/+0
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li1-6/+4
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li2-2/+4
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner1-0/+11
2023-07-10target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner2-25/+28
2023-07-10target/riscv: Use xl instead of mxl for disassembleLIU Zhiwei1-1/+2
2023-07-09target/riscv: Use aesdec_ISB_ISR_IMC_AKRichard Henderson1-91/+10
2023-07-09target/riscv: Use aesenc_SB_SR_MC_AKRichard Henderson1-1/+6
2023-07-09target/riscv: Use aesdec_IMCRichard Henderson1-10/+5
2023-07-09target/riscv: Use aesdec_ISB_ISR_AKRichard Henderson1-1/+6
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