| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-07-02 | target/riscv: configure and turn on vector extension from command line | LIU Zhiwei | 2 | -1/+46 |
| 2020-07-02 | target/riscv: vector compress instruction | LIU Zhiwei | 4 | -0/+64 |
| 2020-07-02 | target/riscv: vector register gather instruction | LIU Zhiwei | 4 | -0/+150 |
| 2020-07-02 | target/riscv: vector slide instructions | LIU Zhiwei | 4 | -0/+155 |
| 2020-07-02 | target/riscv: floating-point scalar move instructions | LIU Zhiwei | 2 | -0/+52 |
| 2020-07-02 | target/riscv: integer scalar move instruction | LIU Zhiwei | 3 | -0/+67 |
| 2020-07-02 | target/riscv: integer extract instruction | LIU Zhiwei | 2 | -0/+117 |
| 2020-07-02 | target/riscv: vector element index instruction | LIU Zhiwei | 4 | -0/+56 |
| 2020-07-02 | target/riscv: vector iota instruction | LIU Zhiwei | 4 | -0/+62 |
| 2020-07-02 | target/riscv: set-X-first mask bit | LIU Zhiwei | 4 | -0/+98 |
| 2020-07-02 | target/riscv: vmfirst find-first-set mask bit | LIU Zhiwei | 4 | -0/+54 |
| 2020-07-02 | target/riscv: vector mask population count vmpopc | LIU Zhiwei | 4 | -0/+55 |
| 2020-07-02 | target/riscv: vector mask-register logical instructions | LIU Zhiwei | 4 | -0/+92 |
| 2020-07-02 | target/riscv: vector widening floating-point reduction instructions | LIU Zhiwei | 4 | -0/+54 |
| 2020-07-02 | target/riscv: vector single-width floating-point reduction instructions | LIU Zhiwei | 4 | -0/+58 |
| 2020-07-02 | target/riscv: vector wideing integer reduction instructions | LIU Zhiwei | 4 | -0/+24 |
| 2020-07-02 | target/riscv: vector single-width integer reduction instructions | LIU Zhiwei | 4 | -0/+133 |
| 2020-07-02 | target/riscv: narrowing floating-point/integer type-convert instructions | LIU Zhiwei | 4 | -0/+103 |
| 2020-07-02 | target/riscv: widening floating-point/integer type-convert instructions | LIU Zhiwei | 4 | -0/+106 |
| 2020-07-02 | target/riscv: vector floating-point/integer type-convert instructions | LIU Zhiwei | 4 | -0/+56 |
| 2020-07-02 | target/riscv: vector floating-point merge instructions | LIU Zhiwei | 4 | -0/+68 |
| 2020-07-02 | target/riscv: vector floating-point classify instructions | LIU Zhiwei | 6 | -30/+107 |
| 2020-07-02 | target/riscv: vector floating-point compare instructions | LIU Zhiwei | 4 | -0/+258 |
| 2020-07-02 | target/riscv: vector floating-point sign-injection instructions | LIU Zhiwei | 4 | -0/+118 |
| 2020-07-02 | target/riscv: vector floating-point min/max instructions | LIU Zhiwei | 4 | -0/+50 |
| 2020-07-02 | target/riscv: vector floating-point square-root instruction | LIU Zhiwei | 4 | -0/+93 |
| 2020-07-02 | target/riscv: vector widening floating-point fused multiply-add instructions | LIU Zhiwei | 4 | -0/+126 |
| 2020-07-02 | target/riscv: vector single-width floating-point fused multiply-add instructions | LIU Zhiwei | 4 | -0/+334 |
| 2020-07-02 | target/riscv: vector widening floating-point multiply | LIU Zhiwei | 4 | -0/+33 |
| 2020-07-02 | target/riscv: vector single-width floating-point multiply/divide instructions | LIU Zhiwei | 4 | -0/+77 |
| 2020-07-02 | target/riscv: vector widening floating-point add/subtract instructions | LIU Zhiwei | 4 | -0/+257 |
| 2020-07-02 | target/riscv: vector single-width floating-point add/subtract instructions | LIU Zhiwei | 4 | -0/+250 |
| 2020-07-02 | target/riscv: vector narrowing fixed-point clip instructions | LIU Zhiwei | 4 | -0/+168 |
| 2020-07-02 | target/riscv: vector single-width scaling shift instructions | LIU Zhiwei | 4 | -0/+148 |
| 2020-07-02 | target/riscv: vector widening saturating scaled multiply-add | LIU Zhiwei | 4 | -0/+243 |
| 2020-07-02 | target/riscv: vector single-width fractional multiply with rounding and satur... | LIU Zhiwei | 4 | -0/+122 |
| 2020-07-02 | target/riscv: vector single-width averaging add and subtract | LIU Zhiwei | 4 | -0/+129 |
| 2020-07-02 | target/riscv: vector single-width saturating add and subtract | LIU Zhiwei | 4 | -0/+444 |
| 2020-07-02 | target/riscv: vector integer merge and move instructions | LIU Zhiwei | 4 | -0/+225 |
| 2020-07-02 | target/riscv: vector widening integer multiply-add instructions | LIU Zhiwei | 4 | -0/+83 |
| 2020-07-02 | target/riscv: vector single-width integer multiply-add instructions | LIU Zhiwei | 4 | -0/+139 |
| 2020-07-02 | target/riscv: vector widening integer multiply instructions | LIU Zhiwei | 4 | -0/+84 |
| 2020-07-02 | target/riscv: vector integer divide instructions | LIU Zhiwei | 4 | -0/+125 |
| 2020-07-02 | target/riscv: vector single-width integer multiply instructions | LIU Zhiwei | 4 | -0/+214 |
| 2020-07-02 | target/riscv: vector integer min/max instructions | LIU Zhiwei | 4 | -0/+122 |
| 2020-07-02 | target/riscv: vector integer comparison instructions | LIU Zhiwei | 4 | -0/+246 |
| 2020-07-02 | target/riscv: vector narrowing integer right shift instructions | LIU Zhiwei | 4 | -0/+123 |
| 2020-07-02 | target/riscv: vector single-width bit shift instructions | LIU Zhiwei | 4 | -0/+165 |
| 2020-07-02 | target/riscv: vector bitwise logical instructions | LIU Zhiwei | 4 | -0/+96 |
| 2020-07-02 | target/riscv: vector integer add-with-carry / subtract-with-borrow instructions | LIU Zhiwei | 4 | -0/+294 |
