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2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt1-2/+2
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel3-4/+92
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2-0/+6
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis4-4/+15
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis6-0/+62
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis2-19/+175
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Remove the hret instructionAlistair Francis2-6/+0
2020-02-27target/riscv: Add hfence instructionsAlistair Francis2-9/+54
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis1-10/+52
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis1-2/+3
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis1-4/+20
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis1-0/+3
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis3-0/+79
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis1-0/+27
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis1-0/+116
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis1-2/+134
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis1-0/+33
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis1-0/+8
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis1-4/+14
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis3-0/+26
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis3-0/+25
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis2-9/+9
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis4-20/+37
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis3-18/+48
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis2-2/+2
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée2-23/+25
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard1-9/+11
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-3/+2
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz1-2/+1
2020-01-24Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell6-11/+5
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung2-3/+2
2020-01-16target/riscv: fsd/fsw doesn't dirty FP stateShihPo Hung2-2/+0
2020-01-16target/riscv: Fix tb->flags FS statusShihPo Hung1-4/+1
2020-01-16riscv: Set xPIE to 1 after xRETYiting Wang1-2/+2
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2-2/+2
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis4-43/+21
2019-11-14remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata1-3/+1
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