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path: root/target/riscv/vector_helper.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-22target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li1-3/+5
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li1-18/+11
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-1/+1
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei1-0/+1
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei1-2/+5
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-1/+2
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang1-0/+21
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang1-0/+191
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang1-0/+183
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-74/+136
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang1-20/+25
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang1-1/+6
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang1-7/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang1-205/+0
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang1-6/+6
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang1-26/+26
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang1-45/+96
2021-12-20target/riscv: rvv-1.0: slide instructionsFrank Chang1-7/+12
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang1-4/+0
2021-12-20target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang1-9/+0
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang1-9/+0
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang1-15/+6
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang1-0/+74
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang1-0/+31
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang1-9/+14
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang1-4/+0
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang1-44/+55
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang1-0/+65
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang1-55/+19
2021-12-20target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang1-4/+4
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang1-56/+42
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang1-130/+69
2021-12-20target/riscv: rvv-1.0: configure instructionsFrank Chang1-1/+13
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang1-125/+0
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang1-1038/+889
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang1-147/+105
2021-12-20target/riscv: Use FIELD_EX32() to extract wd fieldFrank Chang1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-4/+0
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang1-2/+4
2021-05-11target/riscv: Fixup saturate subtract functionLIU Zhiwei1-4/+4
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