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path: root/target/riscv/vector_helper.c
AgeCommit message (Expand)AuthorFilesLines
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li1-0/+11
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li1-0/+6
2023-06-13target/riscv/vector_helper.c: Remove the check for extra tail elementsXiao Wang1-16/+6
2023-06-13target/riscv/vector_helper.c: clean up reference of MTYPEXiao Wang1-5/+1
2023-06-13target/riscv: Fix pointer mask transformation for vector addressWeiwei Li1-1/+1
2023-06-13target/riscv/vector_helper.c: skip set tail when vta is zeroDaniel Henrique Barboza1-3/+8
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-26/+50
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-33/+49
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-78/+81
2023-03-01target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfigDaniel Henrique Barboza1-10/+10
2023-03-01target/riscv/vector_helper.c: create vext_set_tail_elems_1s()Daniel Henrique Barboza1-56/+30
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei1-2/+2
2022-12-14cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster1-21/+7
2022-10-24treewide: Remove the unnecessary space before semicolonBin Meng1-1/+1
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu1-6/+13
2022-09-27target/riscv: rvv-1.0: Simplify vfwredsum codeYang Liu1-46/+10
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen1-2/+24
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen1-0/+11
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen1-0/+26
2022-09-07target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...Yueh-Ting (eop) Chen1-10/+16
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen1-0/+10
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen1-0/+7
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen1-0/+3
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen1-11/+24
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+8
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD1-0/+40
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD1-0/+30
2022-06-10target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD1-0/+20
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD1-196/+244
2022-06-10target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD1-106/+114
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD1-0/+20
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD1-0/+18
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD1-0/+11
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD1-138/+176
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD1-0/+60
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-129/+167
2022-06-10target/riscv: rvv: Rename ambiguous eszeopXD1-38/+38
2022-06-10target/riscv: rvv: Prune redundant access_type parameter passedeopXD1-19/+16
2022-06-10target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD1-567/+565
2022-04-22target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li1-3/+5
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li1-18/+11
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-1/+1
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei1-0/+1
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei1-2/+5
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-1/+2
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang1-0/+21
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
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