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path: root/target/riscv/vector_helper.c
AgeCommit message (Expand)AuthorFilesLines
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-4/+0
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang1-2/+4
2021-05-11target/riscv: Fixup saturate subtract functionLIU Zhiwei1-4/+4
2020-08-28softfloat: Implement the full set of comparisons for float16Kito Cheng1-25/+0
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth1-2/+2
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+26
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+60
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+114
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+24
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+29
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+63
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei1-0/+19
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei1-0/+20
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei1-0/+40
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei1-0/+46
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei1-0/+39
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei1-0/+11
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei1-0/+74
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei1-0/+39
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei1-0/+42
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei1-0/+33
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei1-0/+24
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei1-0/+91
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei1-0/+174
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei1-0/+85
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei1-0/+27
2020-07-02target/riscv: vector floating-point square-root instructionLIU Zhiwei1-0/+43
2020-07-02target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei1-0/+91
2020-07-02target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei1-0/+251
2020-07-02target/riscv: vector widening floating-point multiplyLIU Zhiwei1-0/+22
2020-07-02target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei1-0/+49
2020-07-02target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei1-0/+83
2020-07-02target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei1-0/+111
2020-07-02target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei1-0/+141
2020-07-02target/riscv: vector single-width scaling shift instructionsLIU Zhiwei1-0/+117
2020-07-02target/riscv: vector widening saturating scaled multiply-addLIU Zhiwei1-0/+205
2020-07-02target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei1-0/+107
2020-07-02target/riscv: vector single-width averaging add and subtractLIU Zhiwei1-0/+100
2020-07-02target/riscv: vector single-width saturating add and subtractLIU Zhiwei1-0/+385
2020-07-02target/riscv: vector integer merge and move instructionsLIU Zhiwei1-0/+88
2020-07-02target/riscv: vector widening integer multiply-add instructionsLIU Zhiwei1-0/+45
2020-07-02target/riscv: vector single-width integer multiply-add instructionsLIU Zhiwei1-0/+88
2020-07-02target/riscv: vector widening integer multiply instructionsLIU Zhiwei1-0/+51
2020-07-02target/riscv: vector integer divide instructionsLIU Zhiwei1-0/+74
2020-07-02target/riscv: vector single-width integer multiply instructionsLIU Zhiwei1-0/+163
2020-07-02target/riscv: vector integer min/max instructionsLIU Zhiwei1-0/+71
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei1-0/+123
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei1-0/+14
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei1-0/+79
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei1-0/+51
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