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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-3/+3
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-1/+20
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-2/+2
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner1-0/+8
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson1-4/+0
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson1-0/+19
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+1
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson1-8/+4
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-3/+30
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale1-1/+7
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo1-1/+1
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot1-2/+18
2022-09-06target/riscv: Make translator stop before the end of a pageRichard Henderson1-4/+13
2022-09-06target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson1-1/+9
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson1-9/+9
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson1-9/+2
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson1-0/+2
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD1-0/+2
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-0/+2
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-4/+13
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li1-0/+1
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-0/+7
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-4/+6
2022-03-03target/riscv: add support for zdinxWeiwei Li1-0/+52
2022-03-03target/riscv: add support for zfinxWeiwei Li1-1/+92
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-0/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+1
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+12
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich1-5/+27
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich1-14/+0
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich1-0/+2
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-4/+8
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei1-13/+12
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei1-24/+8
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei1-4/+21
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei1-3/+1
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-0/+2
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-0/+2
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+3