Age | Commit message (Expand) | Author | Files | Lines |
2023-02-07 | target/riscv: fix for virtual instr exception | Deepak Gupta | 1 | -0/+1 |
2023-02-07 | RISC-V: Adding XTheadFmv ISA extension | Christoph Müllner | 1 | -3/+3 |
2023-02-07 | RISC-V: Adding T-Head FMemIdx extension | Christoph Müllner | 1 | -1/+2 |
2023-02-07 | RISC-V: Adding T-Head MemIdx extension | Christoph Müllner | 1 | -1/+20 |
2023-02-07 | RISC-V: Adding T-Head MemPair extension | Christoph Müllner | 1 | -1/+1 |
2023-02-07 | RISC-V: Adding T-Head multiply-accumulate instructions | Christoph Müllner | 1 | -1/+2 |
2023-02-07 | RISC-V: Adding XTheadCondMov ISA extension | Christoph Müllner | 1 | -1/+1 |
2023-02-07 | RISC-V: Adding XTheadBs ISA extension | Christoph Müllner | 1 | -1/+2 |
2023-02-07 | RISC-V: Adding XTheadBb ISA extension | Christoph Müllner | 1 | -2/+2 |
2023-02-07 | RISC-V: Adding XTheadBa ISA extension | Christoph Müllner | 1 | -1/+2 |
2023-02-07 | RISC-V: Adding XTheadSync ISA extension | Christoph Müllner | 1 | -1/+1 |
2023-02-07 | RISC-V: Adding XTheadCmo ISA extension | Christoph Müllner | 1 | -0/+8 |
2023-01-20 | target/riscv: Remove helper_set_rod_rounding_mode | Richard Henderson | 1 | -4/+0 |
2023-01-20 | target/riscv: Introduce helper_set_rounding_mode_chkfrm | Richard Henderson | 1 | -0/+19 |
2023-01-06 | RISC-V: Add Zawrs ISA extension support | Christoph Muellner | 1 | -0/+1 |
2023-01-06 | target/riscv: Set pc_succ_insn for !rvc illegal insn | Richard Henderson | 1 | -8/+4 |
2023-01-06 | target/riscv: Add itrigger support when icount is not enabled | LIU Zhiwei | 1 | -3/+30 |
2023-01-06 | target/riscv: generate virtual instruction exception | Mayuresh Chitale | 1 | -1/+7 |
2022-09-13 | target/riscv: Honour -semihosting-config userspace=on and enable=on | Peter Maydell | 1 | -0/+1 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vv instructions | Yueh-Ting (eop) Chen | 1 | -0/+2 |
2022-09-07 | target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V | Alexey Baturo | 1 | -1/+1 |
2022-09-07 | target/riscv: fix shifts shamt value for rv128c | Frédéric Pétrot | 1 | -2/+18 |
2022-09-06 | target/riscv: Make translator stop before the end of a page | Richard Henderson | 1 | -4/+13 |
2022-09-06 | target/riscv: Add MAX_INSN_LEN and insn_len | Richard Henderson | 1 | -1/+9 |
2022-09-06 | accel/tcg: Add pc and host_pc params to gen_intermediate_code | Richard Henderson | 1 | -2/+3 |
2022-07-03 | target/riscv: Minimize the calls to decode_save_opc | Richard Henderson | 1 | -9/+9 |
2022-07-03 | target/riscv: Remove generate_exception_mtval | Richard Henderson | 1 | -9/+2 |
2022-07-03 | target/riscv: Set env->bins in gen_exception_illegal | Richard Henderson | 1 | -0/+2 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector load / store instructions | eopXD | 1 | -0/+2 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vv instructions | eopXD | 1 | -0/+2 |
2022-05-24 | target/riscv: Set [m|s]tval for both illegal and virtual instruction traps | Anup Patel | 1 | -4/+13 |
2022-04-29 | target/riscv: rvk: add support for zknd/zkne extension in RV32 | Weiwei Li | 1 | -0/+1 |
2022-04-29 | target/riscv: rvk: add support for zbkb extension | Weiwei Li | 1 | -0/+7 |
2022-04-20 | exec/translator: Pass the locked filepointer to disas_log hook | Richard Henderson | 1 | -4/+6 |
2022-03-03 | target/riscv: add support for zdinx | Weiwei Li | 1 | -0/+52 |
2022-03-03 | target/riscv: add support for zfinx | Weiwei Li | 1 | -1/+92 |
2022-03-03 | target/riscv: hardwire mstatus.FS to zero when enable zfinx | Weiwei Li | 1 | -0/+4 |
2022-02-16 | target/riscv: add support for svinval extension | Weiwei Li | 1 | -0/+1 |
2022-02-16 | target/riscv: Add XVentanaCondOps custom extension | Philipp Tomsich | 1 | -0/+12 |
2022-02-16 | target/riscv: iterate over a table of decoders | Philipp Tomsich | 1 | -5/+27 |
2022-02-16 | target/riscv: access configuration through cfg_ptr in DisasContext | Philipp Tomsich | 1 | -14/+0 |
2022-02-16 | target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr | Philipp Tomsich | 1 | -0/+2 |
2022-01-21 | target/riscv: Split pm_enabled into mask and base | LIU Zhiwei | 1 | -4/+8 |
2022-01-21 | target/riscv: Calculate address according to XLEN | LIU Zhiwei | 1 | -13/+12 |
2022-01-21 | target/riscv: Alloc tcg global for cur_pm[mask|base] | LIU Zhiwei | 1 | -24/+8 |
2022-01-21 | target/riscv: Sign extend pc for different XLEN | LIU Zhiwei | 1 | -4/+21 |
2022-01-21 | target/riscv: Sign extend link reg for jal and jalr | LIU Zhiwei | 1 | -3/+1 |
2022-01-21 | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V | Frank Chang | 1 | -0/+2 |
2022-01-21 | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V | Frank Chang | 1 | -0/+2 |
2022-01-08 | target/riscv: Implement the stval/mtval illegal instruction | Alistair Francis | 1 | -0/+3 |