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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-3/+3
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-25/+25
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter1-0/+1
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner1-0/+1
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li1-0/+1
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li1-1/+12
2023-07-10target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner1-25/+2
2023-06-13target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li1-6/+1
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li1-7/+40
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li1-7/+6
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li1-5/+5
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li1-3/+5
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li1-1/+3
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li1-11/+10
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li1-2/+3
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-2/+0
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+4
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-2/+0
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu1-0/+2
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-2/+2
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson1-22/+10
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei1-18/+14
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei1-9/+1
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-8/+12
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-2/+2
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-1/+1
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei1-2/+2
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li1-0/+5
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li1-0/+2
2023-05-05target/riscv: add support for Zca extensionWeiwei Li1-2/+6
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-0/+1
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson1-2/+2
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson1-7/+0
2023-03-05target/riscv: Drop temp_newRichard Henderson1-24/+6
2023-03-05target/riscv: Drop ftemp_newRichard Henderson1-20/+4
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+1
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-1/+2
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+1
2023-03-01target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song1-1/+1
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-3/+3
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-1/+20
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-2/+2
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-1/+2
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