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AgeCommit message (Expand)AuthorFilesLines
2024-03-22target/riscv: rvv: Remove the dependency of Zvfbfmin to ZfbfminMax Chou1-5/+0
2024-03-22target/riscv: do not enable all named features by defaultDaniel Henrique Barboza1-3/+11
2024-03-08target/riscv: Promote svade to a normal extensionAndrew Jones1-0/+6
2024-03-08target/riscv: Gate hardware A/D PTE bit updatingAndrew Jones1-10/+5
2024-03-08target/riscv: add remaining named featuresDaniel Henrique Barboza1-0/+2
2024-03-08target/riscv: add riscv,isa to named featuresDaniel Henrique Barboza1-10/+6
2024-03-08target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()Daniel Henrique Barboza1-0/+1
2024-02-09target/riscv: Validate misa_mxl_max only onceAkihiko Odaki1-23/+0
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki1-6/+6
2024-02-09target/riscv: Remove misa_mxl validationAkihiko Odaki1-12/+3
2024-02-09target/riscv/cpu.c: remove cpu->cfg.vlenDaniel Henrique Barboza1-1/+3
2024-02-09target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza1-4/+0
2024-02-09target/riscv: move 'elen' to riscv_cpu_properties[]Daniel Henrique Barboza1-5/+0
2024-02-09target/riscv: move 'vlen' to riscv_cpu_properties[]Daniel Henrique Barboza1-5/+0
2024-02-09target/riscv: rework 'vext_spec'Daniel Henrique Barboza1-15/+0
2024-02-09target/riscv: rework 'priv_spec'Daniel Henrique Barboza1-29/+0
2024-02-09target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza1-5/+0
2024-02-09target/riscv: Add step to validate 'B' extensionRob Bradford1-0/+33
2024-02-09target/riscv: Add infrastructure for 'B' MISA extensionRob Bradford1-0/+1
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-1/+1
2024-01-19target/riscv: Rename tcg_cpu_FOO() to include 'riscv'Philippe Mathieu-Daudé1-14/+14
2024-01-10target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza1-1/+13
2024-01-10target/riscv: add satp_mode profile supportDaniel Henrique Barboza1-0/+40
2024-01-10target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza1-0/+31
2024-01-10target/riscv: implement svadeDaniel Henrique Barboza1-0/+5
2024-01-10target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza1-0/+9
2024-01-10target/riscv/tcg: validate profiles during finalizeDaniel Henrique Barboza1-0/+69
2024-01-10target/riscv/tcg: honor user choice for G MISA bitsDaniel Henrique Barboza1-25/+48
2024-01-10target/riscv/tcg: add hash table insert helpersDaniel Henrique Barboza1-12/+16
2024-01-10target/riscv/tcg: handle profile MISA bitsDaniel Henrique Barboza1-0/+21
2024-01-10target/riscv/tcg: add riscv_cpu_write_misa_bit()Daniel Henrique Barboza1-14/+18
2024-01-10target/riscv/tcg: add MISA user options hashDaniel Henrique Barboza1-1/+14
2024-01-10target/riscv/tcg: add user flag for profile supportDaniel Henrique Barboza1-0/+80
2024-01-10target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza1-0/+26
2024-01-10target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza1-0/+32
2024-01-10target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza1-4/+9
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li1-0/+5
2023-11-22target/riscv: don't verify ISA compatibility for zicntr and zihpmClément Chigot1-0/+9
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford1-2/+2
2023-11-07target/riscv: Propagate error from PMU setupRob Bradford1-1/+7
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou1-0/+17
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou1-0/+20
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou1-3/+3
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou1-0/+5
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza1-0/+13
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza1-0/+8
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan1-2/+2
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza2-1/+7
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza2-28/+36
2023-11-07target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal1-1/+6
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