riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-07	target/riscv: Add "pmu-mask" property to replace "pmu-num"	Rob Bradford	1	-7/+8
2023-11-07	target/riscv: Use existing PMU counter mask in FDT generation	Rob Bradford	1	-5/+1
2023-11-07	target/riscv: Propagate error from PMU setup	Rob Bradford	1	-10/+9
2023-08-31	target/riscv/pmu: Restrict 'qemu/log.h' include to source	Philippe Mathieu-Daudé	1	-0/+1
2023-05-05	target/riscv: Fix lines with over 80 characters	Weiwei Li	1	-1/+2
2023-05-05	target/riscv: Remove riscv_cpu_virt_enabled()	Weiwei Li	1	-2/+2
2023-05-05	target/riscv: fix invalid riscv,event-to-mhpmcounters entry	Conor Dooley	1	-1/+1
2023-05-05	target/riscv: Simplify type conversion for CPURISCVState	Weiwei Li	1	-3/+3
2023-05-05	target/riscv: Simplify getting RISCVCPU pointer from env	Weiwei Li	1	-4/+4
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra	1	-0/+57
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra	1	-2/+366
2022-07-03	target/riscv: Support mcycle/minstret write operation	Atish Patra	1	-0/+32