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op_helper.c
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Author
Files
Lines
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
1
-0
/
+5
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
1
-27
/
+9
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
1
-86
/
+0
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
1
-12
/
+0
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
1
-13
/
+17
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
1
-7
/
+4
2020-10-22
target/riscv: Fix implementation of HLVX.WU instruction
Georg Kotheimer
1
-3
/
+3
2020-10-22
riscv: Convert interrupt logs to use qemu_log_mask()
Alistair Francis
1
-1
/
+0
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
1
-4
/
+38
2020-08-25
target/riscv: Return the exception from invalid CSR accesses
Alistair Francis
1
-6
/
+12
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
1
-6
/
+2
2020-08-25
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
1
-0
/
+114
2020-06-19
target/riscv: Implement checks for hfence
Alistair Francis
1
-0
/
+13
2020-06-03
target/riscv: Drop support for ISA spec version 1.09.1
Alistair Francis
1
-12
/
+5
2020-03-16
target/riscv: Correctly implement TSR trap
Alistair Francis
1
-1
/
+1
2020-02-27
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Alistair Francis
1
-1
/
+1
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
1
-0
/
+4
2020-02-27
target/riscv: Add Hypervisor trap return support
Alistair Francis
1
-10
/
+52
2020-02-27
target/riscv: Generate illegal instruction on WFI when V=1
Alistair Francis
1
-2
/
+3
2020-01-16
riscv: Set xPIE to 1 after xRET
Yiting Wang
1
-2
/
+2
2019-06-10
target/riscv: Use env_cpu, env_archcpu
Richard Henderson
1
-4
/
+3
2019-05-24
target/riscv: Do not allow sfence.vma from user mode
Jonathan Behrens
1
-3
/
+4
2019-02-11
RISC-V: Use riscv prefix consistently on cpu helpers
Michael Clark
1
-14
/
+14
2019-02-11
RISC-V: Implement mstatus.TSR/TW/TVM
Michael Clark
1
-4
/
+21
2019-01-08
RISC-V: Implement modular CSR helper interface
Michael Clark
1
-598
/
+15
2018-10-17
RISC-V: Update CSR and interrupt definitions
Michael Clark
1
-1
/
+1
2018-10-17
RISC-V: Move non-ops from op_helper to cpu_helper
Michael Clark
1
-34
/
+0
2018-10-17
RISC-V: Allow setting and clearing multiple irqs
Michael Clark
1
-9
/
+15
2018-06-08
RISC-V: Add trailing '\n' to qemu_log() calls
Philippe Mathieu-Daudé
1
-2
/
+4
2018-05-06
RISC-V: No traps on writes to misa,minstret,mcycle
Michael Clark
1
-12
/
+13
2018-05-06
RISC-V: Make mtvec/stvec ignore vectored traps
Michael Clark
1
-6
/
+8
2018-05-06
RISC-V: Add mcycle/minstret support for -icount auto
Michael Clark
1
-2
/
+26
2018-05-06
RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
Michael Clark
1
-14
/
+48
2018-05-06
RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
Michael Clark
1
-2
/
+5
2018-05-06
RISC-V: Hardwire satp to 0 for no-mmu case
Michael Clark
1
-2
/
+5
2018-03-29
RISC-V: Workaround for critical mstatus.FS bug
Michael Clark
1
-2
/
+15
2018-03-07
RISC-V CPU Helpers
Michael Clark
1
-0
/
+669