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op_helper.c
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Author
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Lines
2019-06-10
target/riscv: Use env_cpu, env_archcpu
Richard Henderson
1
-4
/
+3
2019-05-24
target/riscv: Do not allow sfence.vma from user mode
Jonathan Behrens
1
-3
/
+4
2019-02-11
RISC-V: Use riscv prefix consistently on cpu helpers
Michael Clark
1
-14
/
+14
2019-02-11
RISC-V: Implement mstatus.TSR/TW/TVM
Michael Clark
1
-4
/
+21
2019-01-08
RISC-V: Implement modular CSR helper interface
Michael Clark
1
-598
/
+15
2018-10-17
RISC-V: Update CSR and interrupt definitions
Michael Clark
1
-1
/
+1
2018-10-17
RISC-V: Move non-ops from op_helper to cpu_helper
Michael Clark
1
-34
/
+0
2018-10-17
RISC-V: Allow setting and clearing multiple irqs
Michael Clark
1
-9
/
+15
2018-06-08
RISC-V: Add trailing '\n' to qemu_log() calls
Philippe Mathieu-Daudé
1
-2
/
+4
2018-05-06
RISC-V: No traps on writes to misa,minstret,mcycle
Michael Clark
1
-12
/
+13
2018-05-06
RISC-V: Make mtvec/stvec ignore vectored traps
Michael Clark
1
-6
/
+8
2018-05-06
RISC-V: Add mcycle/minstret support for -icount auto
Michael Clark
1
-2
/
+26
2018-05-06
RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
Michael Clark
1
-14
/
+48
2018-05-06
RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
Michael Clark
1
-2
/
+5
2018-05-06
RISC-V: Hardwire satp to 0 for no-mmu case
Michael Clark
1
-2
/
+5
2018-03-29
RISC-V: Workaround for critical mstatus.FS bug
Michael Clark
1
-2
/
+15
2018-03-07
RISC-V CPU Helpers
Michael Clark
1
-0
/
+669