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path: root/target/riscv/op_helper.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li1-0/+9
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-2/+2
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei1-1/+2
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei1-2/+2
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+44
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin1-1/+2
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson1-11/+7
2021-06-08target/riscv: fix wfi exception behaviorJose Martins1-3/+8
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-9/+9
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra1-0/+5
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis1-27/+9
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-86/+0
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-12/+0
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis1-13/+17
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-7/+4
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer1-3/+3
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis1-1/+0
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-4/+38
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis1-6/+12
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-6/+2
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+114
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis1-0/+13
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis1-12/+5
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis1-1/+1
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-1/+1
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+4
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis1-10/+52
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis1-2/+3
2020-01-16riscv: Set xPIE to 1 after xRETYiting Wang1-2/+2
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson1-4/+3
2019-05-24target/riscv: Do not allow sfence.vma from user modeJonathan Behrens1-3/+4
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark1-14/+14
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark1-4/+21
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark1-598/+15
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark1-1/+1
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark1-34/+0
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark1-9/+15
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé1-2/+4
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark1-12/+13
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark1-6/+8
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark1-2/+26
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark1-14/+48
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark1-2/+5
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark1-2/+5
2018-03-29RISC-V: Workaround for critical mstatus.FS bugMichael Clark1-2/+15
2018-03-07RISC-V CPU HelpersMichael Clark1-0/+669
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